Digi NS9750 Bedienungsanleitung

NS9750 Hardware Reference90000624_G

viii Overview...316Ethernet MAC...

System control processor (CP15) registers76 NS9750 Hardware ReferenceFigure 22 shows the format of the FCSE PID register.Figure 22: Process ID regist

www.digiembedded.com77Working with the CPUFigure 23 shows the format of the Context ID register (Rd) transferred during this operation.Figure 23: Cont

DSP78 NS9750 Hardware ReferenceDSPThe ARM926EJ-S processor core provides enhanced DSP capability. Multiply instructions are processed using a single

www.digiembedded.com79Working with the CPU Access permissions for large pages and small pages can be specified separately for each quarter of the pag

Memory Management Unit (MMU)80 NS9750 Hardware Reference Access is permitted and an off-chip access is not required — the cache services the access.

www.digiembedded.com81Working with the CPUAll CP15 MMU registers, except R8: TLB Operations, contain state that can be read using MRC instructions, an

Memory Management Unit (MMU)82 NS9750 Hardware ReferenceThe translation process always begins in the same way — with a level-one fetch. A section-map

www.digiembedded.com83Working with the CPUFigure 25 shows the table walk process.Figure 25: Translating page tablesIndexed bymodifiedvirtualaddressbit

Memory Management Unit (MMU)84 NS9750 Hardware ReferenceFirst-level fetchBits [31:14] of the TTB register are concatenated with bits [31:20] of the M

www.digiembedded.com85Working with the CPU Fine page tables, which have 1024 entries and split the 1 MB that the table describes into 1 KB blocks.Fig

ixRX_D Buffer Descriptor Pointer register ...384Ethernet Interrupt Status register ...

Memory Management Unit (MMU)86 NS9750 Hardware ReferenceSection descriptorA section descriptor provides the base address of a 1 MB block of memory. F

www.digiembedded.com87Working with the CPUCoarse page table descriptorA coarse page table descriptor provides the base address of a page table that co

Memory Management Unit (MMU)88 NS9750 Hardware ReferenceFine page table descriptorA fine page table descriptor provides the base address of a page ta

www.digiembedded.com89Working with the CPUTranslating section referencesFigure 31 shows the complete section translation sequence.Figure 31: Section t

Memory Management Unit (MMU)90 NS9750 Hardware ReferenceFigure 32: Second-level descriptorA second-level descriptor defines a tiny, small, or large p

www.digiembedded.com91Working with the CPUThe two least significant bits of the second-level descriptor indicate the descriptor type; see Table 38.Not

Memory Management Unit (MMU)92 NS9750 Hardware ReferenceFigure 33: Large page translation from a coarse page tableBecause the upper four bits of the

www.digiembedded.com93Working with the CPUIf the large page descriptor is included in a fine page table, the high-order six bits of the page index and

Memory Management Unit (MMU)94 NS9750 Hardware ReferenceIf a small page descriptor is included in a fine page table, the upper two bits of the page i

www.digiembedded.com95Working with the CPUPage translation involves one additional step beyond that of a section translation. The first-level descript

x CardBus interrupts...465Chapter 8: BBus Bridge ...

Memory Management Unit (MMU)96 NS9750 Hardware ReferenceThe access control mechanisms of the MMU detect the conditions that produce these faults. If

www.digiembedded.com97Working with the CPUNotes: Alignment faults can write either 0b0001 or 0b0011 into Fault Status register [3:0]. Invalid values

Memory Management Unit (MMU)98 NS9750 Hardware ReferenceCompatibility issues To enable code to be ported easily to future architectures, it is recom

www.digiembedded.com99Working with the CPUFault checking sequenceThe sequence the MMU uses to check for access faults is different for sections and pa

Memory Management Unit (MMU)100 NS9750 Hardware ReferenceFigure 36: Sequence for checking faultsThe conditions that generate each of the faults are d

www.digiembedded.com101Working with the CPUAlignment faultsIf alignment fault checking is enabled (the A bit in the R1: Control register is set; see &

Memory Management Unit (MMU)102 NS9750 Hardware ReferencePermission faultsIf the two-bit domain field returns client (01), access permissions are che

www.digiembedded.com103Working with the CPU Nonbuffered writes Noncached read-lock-write (SWP) sequenceFor a read-lock-write (SWP) sequence, the wri

Memory Management Unit (MMU)104 NS9750 Hardware ReferenceDisabling the MMUClear bit 0 (the M bit) in the R1: Control register to disable the MMU.Note

www.digiembedded.com105Working with the CPUtimes. To guarantee coherency if a level one descriptor is modified in main memory, either an invalidate-TL

xiDMA buffer descriptor ...504DMA channel assignments ...

Caches and write buffer106 NS9750 Hardware Reference The DCache stores the Physical Address Tag (PA tag) corresponding to each DCache entry in the t

www.digiembedded.com107Working with the CPUEnabling the cachesOn reset, the ICache and DCache entries all are invalidated and the caches disabled. The

Caches and write buffer108 NS9750 Hardware ReferenceTable 46 gives the page table C and B bit settings for the DCache (R1: Control register C bit = M

www.digiembedded.com109Working with the CPUCache MVA and Set/Way formatsThis section shows how the MVA and set/way formats of ARM926EJ-S caches map to

Caches and write buffer110 NS9750 Hardware ReferenceFigure 38 shows the ARM926EJ-S cache format. Figure 38: ARM926EJ-S cache associativityThe followi

www.digiembedded.com111Working with the CPUFigure 39 shows the set/way/word format for ARM926EJ-S caches.Figure 39: ARM926EJ-S cache set/way/word form

Noncachable instruction fetches112 NS9750 Hardware ReferenceSelf-modifying codeA four-word buffer holds speculatively fetched instructions. Only sequ

www.digiembedded.com113Working with the CPUInstruction Memory BarrierWhenever code is treated as data — for example, self-modifying code or loading co

Instruction Memory Barrier114 NS9750 Hardware Referencerecommended that either a nonbuffered store (STR) or a noncached load (LDR) be used to trigger

115Memory ControllerCHAPTER 4The Multiport Memory Controller is an AMBA-compliant system-on-chip (SoC) peripheral that connects to the Advanced High-p

xii Flow charts ...556Master module (normal mode, 16-bit)...

Features116 NS9750 Hardware ReferenceFeaturesThe memory controller provides these features: AMBA 32-bit AHB compliancy. Dynamic memory interface su

www.digiembedded.com117Memory Controller Support for all AHB burst types.  Little and big endian support.Note:Synchronous static memory devices (syn

Features118 NS9750 Hardware ReferenceLow-power operationIn many systems, the contents of the memory system have to be maintained during low-power sle

www.digiembedded.com119Memory ControllerChip select 1 memory configurationYou can configure the memory width and chip select polarity of static memory

Features120 NS9750 Hardware Reference8 More boot, initialization, or application code is executed.Example: Boot from flash, SDRAM remapped after boot

www.digiembedded.com121Memory ControllerStatic memory controllerTable 48 shows configurations for the static memory controller with different types of

Static memory controller122 NS9750 Hardware ReferenceWrite protectionEach static memory chip select can be configured for write-protection. SRAM usua

www.digiembedded.com123Memory ControllerMemory mapped peripheralsSome systems use external peripherals that can be accessed using the static memory in

Static memory controller124 NS9750 Hardware Reference "Static Memory Page Mode Read Delay 0–3 registers" on page 237 (StaticWaitPage[n])

www.digiembedded.com125Memory ControllerROM, SRAM, and FlashThe memory controller uses the same read timing control for ROM, SRAM, and flash devices.

xiiiLCDPalette register...595Interrupts ...

Static memory controller126 NS9750 Hardware ReferenceFigure 42 shows an external memory read transfer with two wait states (WA ITR D= 2). Seven AHB c

www.digiembedded.com127Memory ControllerFigure 43 shows an external memory read transfer with two output enable delay states (WAI TO EN= 2). Seven AHB

Static memory controller128 NS9750 Hardware ReferenceFigure 44 shows external memory read transfers with zero wait states (WA IT RD =0 ). These trans

www.digiembedded.com129Memory ControllerTable 55 provides the timing parameters. Table 56 describes the transactions for Figure 44.Figure 44: External

Static memory controller130 NS9750 Hardware ReferenceFigure 45 shows a burst of zero wait state reads with the length specified. Because the length o

www.digiembedded.com131Memory ControllerFigure 46 shows a burst of two wait state reads with the length specified. The WA IT RD value is used for all

Static memory controller132 NS9750 Hardware ReferenceFigure 46: External memory 2 wait states fixed length burst read timing diagramTiming parameter

www.digiembedded.com133Memory ControllerAsynchronous page mode readThe memory controller supports asynchronous page mode read of up to four memory tra

Static memory controller134 NS9750 Hardware ReferenceFigure 47: External memory page mode read transfer timing diagramTiming parameter ValueWAITRD 2W

www.digiembedded.com135Memory ControllerFigure 48 shows a 32-bit read from an 8-bit page mode ROM device, causing four burst reads to be performed. A

xiv Serial port control and status registers ...650Serial Channel B/A/C/D Control Register A ...

Static memory controller136 NS9750 Hardware ReferenceStatic memory write controlWrite enable programming delayThe delay between the assertion of the

www.digiembedded.com137Memory Controllerdeasserted a cycle before the chip select, at the end of the transfer. BLSOUT_n (byte lane signal) has the sam

Static memory controller138 NS9750 Hardware ReferenceFigure 50 shows a single external memory write transfer with two wait states (WA IT WR =2). One

www.digiembedded.com139Memory ControllerFigure 50: External memory 2 wait state write timing diagramTiming parameter ValueWAITRD N/AWAITOEN N/AWAITPAG

Static memory controller140 NS9750 Hardware ReferenceFigure 51 shows a single external memory write transfer with two write enable delay states (WAI

www.digiembedded.com141Memory ControllerFigure 52 shows two external memory write transfers with zero wait states (WA IT WR =0). Four AHB wait states

Static memory controller142 NS9750 Hardware ReferenceFigure 52: External memory 2 0 wait writes timing diagramTiming parameter ValueWAITRD N/AWAITOEN

www.digiembedded.com143Memory ControllerFlash memoryWrite timing for flash memory is the same as for SRAM devices.Bus turnaroundThe memory controller

Static memory controller144 NS9750 Hardware ReferenceFigure 53: Read followed by write (both 0 wait) with no turnaroundTiming parameter ValueWAITRD 0

www.digiembedded.com145Memory ControllerFigure 54 shows a zero wait write followed by a zero wait read with default turnaround between the transfers o

xvPin Interrupt Mask register...700Pin Interrupt Control register...

Static memory controller146 NS9750 Hardware ReferenceTable 75 provides the timing parameters. Table 76 describes the transactions for Figure 54.Figur

www.digiembedded.com147Memory ControllerFigure 55 shows a zero wait read followed by a zero wait write with two turnaround cycles added. The standard

Static memory controller148 NS9750 Hardware ReferenceTable 77 provides the timing parameters. Table 78 describes the transactions for Figure 55.Figur

www.digiembedded.com149Memory ControllerByte lane controlThe memory controller generates the byte lane control signals BLSOUT[3:0]_n according to thes

Static memory controller150 NS9750 Hardware Referencepartitioned memory devices" on page 150 and "Memory banks constructed from 8-bit or no

www.digiembedded.com151Memory ControllerFigure 56: Memory banks constructed from 8-bit memoryFigure 56 shows 8-bit memory configuring memory banks tha

Static memory controller152 NS9750 Hardware ReferenceFigure 58: Memory banks constructed from 32-bit memoryFigure 59 shows connections for a typical

www.digiembedded.com153Memory ControllerFigure 59: Typical memory connection diagram (1)DATAOUT[31:0]DATAOUT[31:0]DATAOUT[31:16]DATAOUT[15:0]DATAOUT[3

Static memory controller154 NS9750 Hardware ReferenceByte lane control and databus steeringFor little and big endian configurations, address right-ju

www.digiembedded.com155Memory ControllerAccess: Read, little endian, 16-bit external busExternal data mapping on to system databusInternal transfer wi

xvi HcHCCA register ...739HcPeriodCurrentED register...

Static memory controller156 NS9750 Hardware ReferenceByte 000 10 1011 - [23:16] - -Byte 000 01 1101 - - [15:8] -Byte 000 00 1110 ---[7:0]Access: Writ

www.digiembedded.com157Memory ControllerAccess: Write, little endian, 16-bit external busSystem data mapping on to external databusInternal transfer w

Static memory controller158 NS9750 Hardware ReferenceByte 000 01 1101 - - [15:8] -Byte 000 00 1110 ---[7:0]Access: Read, big endian, 8-bit external b

www.digiembedded.com159Memory ControllerAccess: Read, big endian, 16-bit external busExternal data mapping on to system databusInternal transfer width

Static memory controller160 NS9750 Hardware ReferenceByte 000 01 -- 1011 - [23:16] - -Byte 000 00 -- 0111 [31:24] - - -Access: Write, big endian, 8-b

www.digiembedded.com161Memory ControllerAccess: Write, big endian, 16-bit external busSystem data mapping on to external databusInternal transfer widt

Dynamic memory controller162 NS9750 Hardware ReferenceDynamic memory controllerWrite protectionEach dynamic memory chip select can be configured for

www.digiembedded.com163Memory ControllerWord transfers are the widest transfers supported by the memory controller. Any access tried with a size large

Dynamic memory controller164 NS9750 Hardware Referencedevices. The row-bank-column address mapping scheme allows memory accesses to be performed effi

www.digiembedded.com165Memory ControllerTable 92 shows the outputs from the memory controller and the corresponding inputs to the 16M SDRAM (2Mx8, pin

xviiMemory timing ...795SDRAM burst read (16-bit)...

Dynamic memory controller166 NS9750 Hardware ReferenceTable 93 shows the outputs from the memory controller and the corresponding inputs to the 64M S

www.digiembedded.com167Memory ControllerTable 94 shows the outputs from the memory controller and the corresponding inputs to the 64M SDRAM (4Mx16, pi

Dynamic memory controller168 NS9750 Hardware ReferenceTable 95 shows the outputs from the memory controller and the corresponding inputs to the 64 M

www.digiembedded.com169Memory ControllerTable 97 shows the outputs from the memory controller and the corresponding inputs to the 64M SDRAM (8Mx16, pi

Dynamic memory controller170 NS9750 Hardware ReferenceTable 98 shows the outputs from the memory controller and the corresponding inputs to the 128M

www.digiembedded.com171Memory ControllerTable 99 shows the outputs from the memory controller and the corresponding inputs to the 256M SDRAM (8Mx32, p

Dynamic memory controller172 NS9750 Hardware ReferenceTable 100 shows the outputs from the memory controller and the corresponding inputs to the 256M

www.digiembedded.com173Memory ControllerTable 102 shows the outputs from the memory controller and the corresponding inputs to the 512M SDRAM (32Mx16,

Dynamic memory controller174 NS9750 Hardware ReferenceTable 103 shows the outputs from the memory controller and the corresponding inputs to the 512M

www.digiembedded.com175Memory Controller32-bit wide databus address mappings (BRC)Table 104 through Table 116 show 32-bit wide databus address mapping

xviii SPI master mode 0 and 1: 2-byte transfer ...829SPI master mode 2 and 3: 2-byte transfer ...

Dynamic memory controller176 NS9750 Hardware ReferenceTable 105 shows the outputs from the memory controller and the corresponding inputs to the 16M

www.digiembedded.com177Memory ControllerTable 107 shows the outputs from the memory controller and the corresponding inputs to the 64M SDRAM (4Mx16, p

Dynamic memory controller178 NS9750 Hardware ReferenceTable 108 shows the outputs from the memory controller and the corresponding inputs to the 64M

www.digiembedded.com179Memory ControllerTable 109 shows the outputs from the memory controller and the corresponding inputs to the 128M SDSRAM (4Mx32,

Dynamic memory controller180 NS9750 Hardware ReferenceTable 110 shows the outputs from the memory controller and the corresponding inputs to the 128M

www.digiembedded.com181Memory ControllerTable 112 shows the outputs from the memory controller and the corresponding inputs to the 256M SDRAM (8Mx32,

Dynamic memory controller182 NS9750 Hardware ReferenceTable 113 shows the outputs from the memory controller and the corresponding inputs to the 256M

www.digiembedded.com183Memory ControllerTable 114 shows the outputs from the memory controller and the corresponding inputs to the 256M SDRAM (32Mx8,

Dynamic memory controller184 NS9750 Hardware ReferenceTable 115 shows the outputs from the memory controller and the corresponding inputs to the 512M

www.digiembedded.com185Memory Controller16-bit wide databus address mappings, SDRAM (RBC)Table 117 through Table 126 show 16-bit wide databus address

Using This Guide xixReview this section for basic information about the guide you are using, as well as general support and contact information. This

Dynamic memory controller186 NS9750 Hardware ReferenceTable 118 shows the outputs from the memory controller and the corresponding inputs to the 16M

www.digiembedded.com187Memory ControllerTable 119 shows the outputs from the memory controller and the corresponding inputs to the 64M SDRAM (4Mx16, p

Dynamic memory controller188 NS9750 Hardware ReferenceTable 120 shows the outputs from the memory controller and the corresponding inputs to the 64M

www.digiembedded.com189Memory ControllerTable 122 shows the outputs from the memory controller and the corresponding inputs to the 128M SDRAM (16Mx8,

Dynamic memory controller190 NS9750 Hardware ReferenceTable 123 shows the outputs from the memory controller and the corresponding inputs to the 256M

www.digiembedded.com191Memory ControllerTable 124 shows the outputs from the memory controller and the corresponding inputs to the 256M SDRAM (32Mx8,

Dynamic memory controller192 NS9750 Hardware ReferenceTable 125 shows the outputs from the memory controller and the corresponding inputs to the 512M

www.digiembedded.com193Memory ControllerTable 126 shows the outputs from the memory controller and the corresponding inputs to the 512M SDRAM (64Mx8,

Dynamic memory controller194 NS9750 Hardware ReferenceTable 128 shows the outputs from the memory controller and the corresponding inputs to the 16M

www.digiembedded.com195Memory ControllerTable 129 shows the outputs from the memory controller and the corresponding inputs to the 64M SDRAM (4Mx16, p

xx NS9750 Hardware ReferenceWhat’s in this guideThis table shows where you can find specific information in the printed guides.To read about See VolN

Dynamic memory controller196 NS9750 Hardware ReferenceTable 130 shows the outputs from the memory controller and the corresponding inputs to the 64M

www.digiembedded.com197Memory ControllerTable 131 shows the outputs from the memory controller and the corresponding inputs to the 128M SDRAM (8Mx16,

Dynamic memory controller198 NS9750 Hardware ReferenceTable 133 shows the outputs for the memory controller and the corresponding inputs to the 256M

www.digiembedded.com199Memory ControllerTable 134 shows the outputs for the memory controller and the corresponding inputs to the 256M SDRAM (32Mx8, p

Dynamic memory controller200 NS9750 Hardware ReferenceTable 135 shows the outputs from the memory controller and the corresponding inputs to the 512M

www.digiembedded.com201Memory ControllerTable 136 shows the outputs from the memory controller and the corresponding inputs to the 512M SDRAM (64Mx8,

Registers202 NS9750 Hardware ReferenceRegistersThe external memory is accessed using the AHB memory interface ports. Addresses are not fixed, but are

www.digiembedded.com203Memory ControllerA070 0048 DynamictRC Dynamic Memory Active to Active Command Period (tRC)A070 004C DynamictRFC Dynamic Memory

Registers204 NS9750 Hardware ReferenceReset valuesReset values will be noted as appropriate in the Description column of each register table, rather

www.digiembedded.com205Memory ControllerControl registerAddress: A070 0000The Control register controls the memory controller operation. The control b

www.digiembedded.comxxiConventions used in this guideThis table describes the typographic conventions used in this guide:Related documentation NS9750

Registers206 NS9750 Hardware ReferenceD01 R/W ADDM Address mirror0 Normal memory map1 Reset memory map. Static memory chip select 1 is mirrored onto

www.digiembedded.com207Memory ControllerStatus registerAddress: A070 0004The Status register provides memory controller status information.Register bi

Registers208 NS9750 Hardware ReferenceThe Configuration register configures memory controller operation. It is recommended that this register be modi

www.digiembedded.com209Memory ControllerThe Dynamic Memory Control register controls dynamic memory operation. The control bits can be changed during

Registers210 NS9750 Hardware ReferenceDynamic Memory Refresh Timer registerAddress: A070 0024The Dynamic Memory Refresh Timer register configures dyn

www.digiembedded.com211Memory ControllerRegister bit assignmentExamplesGeneric formula: DynamicRefresh = (((tREF / #rows) * speed grade) / 32)For 4k r

Registers212 NS9750 Hardware ReferenceDynamic Memory Read Configuration registerAddress: A070 0028The Dynamic Memory Read Configuration register allo

www.digiembedded.com213Memory ControllerDynamic Memory Precharge Command Period registerAddress: A070 0030The Dynamic Memory Precharge Command Period

Registers214 NS9750 Hardware ReferenceDynamic Memory Active to Precharge Command Period registerAddress: A070 0034The Dynamic Memory Active to Precha

www.digiembedded.com215Memory ControllerDynamic Memory Self-refresh Exit Time registerAddress: A070 0038The Dynamic Memory Self-refresh Exit Time regi

xxii NS9750 Hardware ReferenceBe aware that if you see differences between the documentation you received in your package and the documentation on th

Registers216 NS9750 Hardware ReferenceDynamic Memory Last Data Out to Active Time registerAddress: A070 003CThe Dynamic Memory Last Data Out to Activ

www.digiembedded.com217Memory ControllerDynamic Memory Data-in to Active Command Time registerAddress: A070 0040The Dynamic Memory Data-in to Active C

Registers218 NS9750 Hardware ReferenceDynamic Memory Write Recovery Time registerAddress: A070 0044The Dynamic Memory Write Recovery Time register al

www.digiembedded.com219Memory ControllerDynamic Memory Active to Active Command Period registerAddress: A070 0048The Dynamic Memory Active to Active C

Registers220 NS9750 Hardware ReferenceDynamic Memory Auto Refresh Period registerAddress: A070 004CThe Dynamic Memory Auto Refresh Period register al

www.digiembedded.com221Memory ControllerDynamic Memory Exit Self-refresh registerAddress: A070 0050The Dynamic memory Exit Self-refresh register allow

Registers222 NS9750 Hardware ReferenceDynamic Memory Active Bank A to Active Bank B Time registerAddress: A070 0054The Dynamic Memory Active Bank A t

www.digiembedded.com223Memory ControllerDynamic Memory Load Mode register to Active Command Time registerAddress: A070 0058The Dynamic Memory Load Mod

Registers224 NS9750 Hardware ReferenceStatic Memory Extended Wait registerAddress: A070 0080The Static Memory Extended Wait register times long stati

www.digiembedded.com225Memory ControllerExampleStatic memory read/write time = 16 usCLK frequency = 50 MHzThis value must be programmed into the Stati

1About NS9750CHAPTER 1The Digi NS9750 is a single chip 0.13μm CMOS network-attached processor. This chapter provides an overview of the NS9750, which

Registers226 NS9750 Hardware ReferenceTable 157 shows address mapping for the Dynamic Memory Configuration 0-3 registers. Address mappings that are n

www.digiembedded.com227Memory Controller0 0 011 00256 Mb (32Mx8), 4 banks, row length=13, column length=100 0 011 01256 Mb (16Mx16), 4 banks, row leng

Registers228 NS9750 Hardware ReferenceA chip select can be connected to a single memory device; in this situation, the chip select data bus width is

www.digiembedded.com229Memory ControllerDynamic Memory RAS and CAS Delay 0–3 registersAddress: A070 0104 / 0124 / 0144 / 0164The Dynamic Memory RAS an

Registers230 NS9750 Hardware ReferenceStatic Memory Configuration 0–3 registersAddress: A070 0200 / 0220 / 0240 / 0260The Static Memory Configuration

www.digiembedded.com231Memory ControllerD08 R/W EW Extended wait0 Extended wait disabled (reset value on reset_n)Extended wait enabledExtended wait us

Registers232 NS9750 Hardware ReferenceD07 R/W PB Byte lane state0 For reads, all bits in byte_lane_sel_n[3:0] are high. For writes, the respective ac

www.digiembedded.com233Memory ControllerNote:Synchronous burst mode memory devices are not supported.D03 R/W PM Page mode0 Disabled (reset on reset_n)

Registers234 NS9750 Hardware ReferenceStatic Memory Write Enable Delay 0–3 registersAddress: A070 0204 / 0224 / 0244 / 0264The Static Memory Write En

www.digiembedded.com235Memory ControllerStatic Memory Output Enable Delay 0–3 registersAddress: A070 0208 / 0228 / 0248 / 0268The Static Memory Output

NS9750 Features2 NS9750 Hardware ReferenceNS9750 FeaturesThe NS9750 uses an ARM926EJ-S core as its CPU, with MMU, DSP extensions, Jazelle Java accele

Registers236 NS9750 Hardware ReferenceStatic Memory Read Delay 0–3 registersAddress: A070 020C / 022C / 024C / 026CThe Static Memory Read Delay 0–3 r

www.digiembedded.com237Memory ControllerStatic Memory Page Mode Read Delay 0–3 registersAddress: A070 0210 / 0230 / 0250 / 0270The Static Memory Page

Registers238 NS9750 Hardware ReferenceStatic Memory Write Delay 0–3 registersAddress: A070 0214 / 0234 / 0254 / 0274The Static Memory Write Delay 0–3

www.digiembedded.com239Memory ControllerStatic Memory Turn Round Delay 0–3 registersAddress: A070 0218 / 0238 / 0258 / 0278The Static Memory Turn Roun

Registers240 NS9750 Hardware Reference

www.digiembedded.com241Memory Controller

Registers242 NS9750 Hardware Reference

www.digiembedded.com243Memory Controller

Registers244 NS9750 Hardware Reference

www.digiembedded.com245Memory Controller

www.digiembedded.com3About NS9750 Burst mode support with automatic data width adjustment Two external DMA channels for external peripheral supportS

Registers246 NS9750 Hardware Reference

www.digiembedded.com247Memory Controller

Registers248 NS9750 Hardware Reference

www.digiembedded.com249Memory Controller

Registers250 NS9750 Hardware Reference

www.digiembedded.com251Memory Controller

253System Control ModuleCHAPTER 5The System Control Module configures and oversees system operations for the NS9750, and defines both the NS9750 AHB a

System Control Module features254 NS9750 Hardware ReferenceSystem Control Module featuresThe System Control Module uses the following to configure an

www.digiembedded.com255System Control Modulemet. See "Arbiter configuration examples" on page 258 for information about configuring the AHB

NS9750 Features4 NS9750 Hardware ReferenceFlexible LCD controller Supports most commercially available displays:– Active Matrix color TFT displays:U

System bus arbiter256 NS9750 Hardware Reference Main arbiter. Contains a 16-entry Bus Request Configuration (BRC) register. Each BRC entry represent

www.digiembedded.com257System Control ModuleOwnershipOwnership of the data bus is delayed from ownership of the address/control bus. When hready indic

System bus arbiter258 NS9750 Hardware ReferenceSPLIT transfersA SPLIT transfer occurs when a slave is not ready to perform the transfer. The slave sp

www.digiembedded.com259System Control ModuleExample 1Since the 20 Mbyte per master guarantee meets the requirements of all masters, the AHB arbiter wi

System bus arbiter260 NS9750 Hardware ReferenceThe available bandwidth per master is calculated using this formula:Bandwidth per master: = [(100MHz/2

www.digiembedded.com261System Control ModuleAddress decodingA central address decoder provides a select signal — hsel_x — for each slave on the bus. T

Address decoding262 NS9750 Hardware ReferenceThe internal registers, unlike system memory, can be accessed only in privileged access mode. Privileged

www.digiembedded.com263System Control ModuleProgrammable timersNS9750 provides 18 programmable timers:  Software watchdog timer Bus monitor timer 1

Programmable timers264 NS9750 Hardware Referencein the appropriate Timer Control register (see "Timer 0–15 Control registers" on page 301).

www.digiembedded.com265System Control Module// This command file initializes the debugger local variables that are// used by the user defined On-Stop

www.digiembedded.com5About NS9750 Internal or external clock support, digital PLL for RX clock extraction 4 receive-side data match detectors 2 ded

Programmable timers266 NS9750 Hardware Reference// Examples://// ew MAJIC_ON_STOP_CMD = 1, @$ucd_rd8, FFF00003//// Defines an On-Stop command that re

www.digiembedded.com267System Control ModuleInterrupt controllerThe interrupt system is a simple two-tier priority scheme. Two lines access the CPU co

Interrupt controller268 NS9750 Hardware ReferenceFigure 61: Interrupt controller block diagramThe IRQ interrupts are enabled by the respective enabli

www.digiembedded.com269System Control ModuleThe NS9750 interrupt sources are assigned as shown:Interrupt ID Interrupt source0 Watchdog Timer1 AHB Bus

Interrupt controller270 NS9750 Hardware ReferenceVectored interrupt controller (VIC) flow A vectored interrupt controller allows a reasonable interru

www.digiembedded.com271System Control ModuleSystem attributesSystem software can configure these NS9750 system attributes: Little endian/big endian m

System attributes272 NS9750 Hardware ReferenceFigure 62 shows how the PLL clock is used to provide the NS9750 system clocks.Figure 62: NS9750 system

www.digiembedded.com273System Control ModuleTable 168 indicates how each bit is used to configure the powerup settings, where 1 indicates the internal

System attributes274 NS9750 Hardware Referencereset_done Bootup mode0 Boot from SDRAM using serial SPI EEPROM1 Boot from flash/ROMgpio[19] PLL BP (PL

www.digiembedded.com275System Control Module10001 2110110 2010111 1910100 1810101 1701010 1601011 1501000 1401001 1301110 1201111 1101100 1001101 9000

Part number/version: 90000624_GRelease date: March 2008www.digiembedded.comNS9750 Hardware Reference

NS9750 Features6 NS9750 Hardware Reference Each DMA channel supports memory-to-memory transfersPower management (patent pending) Power save during

System configuration registers276 NS9750 Hardware ReferenceThere are 32 additional GPIO pins that are used to create a general purpose, user-defined

www.digiembedded.com277System Control ModuleA090 0048 Timer 1 Reload Count registerA090 004C Timer 2 Reload Count registerA090 0050 Timer 3 Reload Cou

System configuration registers278 NS9750 Hardware ReferenceA090 00B4 Timer 12 Read registerA090 00B8 Timer 13 Read registerA090 00BC Timer 14 Read re

www.digiembedded.com279System Control ModuleA090 0120 Interrupt Vector Address Register Level 23A090 0124 Interrupt Vector Address Register Level 24A0

System configuration registers280 NS9750 Hardware ReferenceA090 018C Active Interrupt Level registerA090 0190 Timer 0 Control registerA090 0194 Timer

www.digiembedded.com281System Control ModuleA090 01F8 System Memory Chip Select 1 Static Memory BaseA090 01FC System Memory Chip Select 1 Static Memor

System configuration registers282 NS9750 Hardware ReferenceAHB Arbiter Gen Configuration registerAddress: A090 0000The AHB Arbiter Gen Configuration

www.digiembedded.com283System Control ModuleBRC0, BRC1, BRC2, and BRC3 registersAddress: A090 0004 / 0008 / 000C / 0010The BRC[0:3] registers control

System configuration registers284 NS9750 Hardware ReferenceTimer 0–15 Reload Count registersAddress: A090 0044 (Timer 0) / 0048 / 004C / 0050 / 0054

www.digiembedded.com285System Control ModuleTimer 0–15 Read registerAddress: A090 0084 / 0088 / 008C / 0090 / 0094 / 0098 / 009C / 00A0 / 00A4 / 00A8

www.digiembedded.com7About NS9750External interrupts 4 external programmable interrupts– Rising or falling edge-sensitive– Low level- or high level-s

System configuration registers286 NS9750 Hardware ReferenceRegister bit assignmentInt (Interrupt) Config (Configuration) registers (0–31)Address: A09

www.digiembedded.com287System Control ModuleRegister bit assignmentBIts Access Mnemonic Reset DefinitionD07 R/W IE 0x0 Interrupt enable0 Interrupt is

System configuration registers288 NS9750 Hardware ReferenceISRADDR registerAddress: A090 0164The ISRADDR register provides the current ISRADDR value.

www.digiembedded.com289System Control ModuleInterrupt Status Active Address: A090 0168The Interrupt Status Active register shows the current interrupt

System configuration registers290 NS9750 Hardware ReferenceInterrupt Status RawAddress: A090 016CThe Interrupt Status Raw register shows all current

www.digiembedded.com291System Control ModuleTimer Interrupt Status registerAddress: A090 0170The Timer Interrupt Status register shows all current tim

System configuration registers292 NS9750 Hardware ReferenceRegister bit assignmentBits Access Mnemonic Reset DescriptionD31:08 N/A Reserved N/A N/AD0

www.digiembedded.com293System Control ModuleSoftware Watchdog Timer registerAddress: A090 0178The Software Watchdog Timer register services the watchd

System configuration registers294 NS9750 Hardware ReferenceRegister bit assignmentBits Access Mnemonic Reset DescriptionD31:10 N/A Reserved N/A N/AD0

www.digiembedded.com295System Control ModuleReset and Sleep Control registerAddress: A090 0180The Reset and Sleep Control register resets each module

System-level interfaces8 NS9750 Hardware ReferenceSystem-level interfacesFigure 1 shows the NS9750 system-level interfaces.Figure 1: System-level har

System configuration registers296 NS9750 Hardware ReferenceMiscellaneous System Configuration and Status registerAddress: A090 0184D18 R/W SMWE 0x0 S

www.digiembedded.com297System Control ModuleThe Miscellaneous System Configuration and Status register configures miscellaneous system configuration b

System configuration registers298 NS9750 Hardware ReferenceD09:08 R CS1DWHW strap boot_strap[4], boot_strap[3]Chip select 1 data width HW strap setti

www.digiembedded.com299System Control ModulePLL Configuration registerAddress: A090 0188The PLL Configuration register configures the PLL. Register bi

System configuration registers300 NS9750 Hardware ReferenceD20:16 R PLLNDHW strap gpio[17], gpio[12], gpio[10], gpio[8], gpio[4]PLL ND status[4:0]Sta

www.digiembedded.com301System Control ModuleActive Interrupt Level Status registerAddress: A090 018CThe Active Interrupt Level Status register shows t

System configuration registers302 NS9750 Hardware ReferenceRegister bit assignmentBits Access Mnemonic Reset Description31:16 N/A Reserved N/A N/AD15

www.digiembedded.com303System Control ModuleSystem Memory Chip Select 0 Dynamic Memory Base and Mask registersAddress: A090 01D0 / 01D4These control r

System configuration registers304 NS9750 Hardware ReferenceRegister bit assignmentSystem Memory Chip Select 1 Dynamic Memory Base and Mask registersA

www.digiembedded.com305System Control ModuleRegister bit assignmentSystem Memory Chip Select 2 Dynamic Memory Base and Mask registersAddress: A090 01E

www.digiembedded.com9About NS9750– 1284 port– Up to 24-bit TFT or STN color and monochrome LCD controller– Two external DMA channels– Four external in

System configuration registers306 NS9750 Hardware ReferenceRegister bit assignmentSystem Memory Chip Select 3 Dynamic Memory Base and Mask registersA

www.digiembedded.com307System Control ModuleRegister bit assignmentSystem Memory Chip Select 0 Static Memory Base and Mask registersAddress: A090 01F0

System configuration registers308 NS9750 Hardware ReferenceRegister bit assignmentSystem Memory Chip Select 1 Static Memory Base and Mask registersAd

www.digiembedded.com309System Control ModuleRegister bit assignmentSystem Memory Chip Select 2 Static Memory Base and Mask registersAddress: A090 0200

System configuration registers310 NS9750 Hardware ReferenceRegister bit assignmentSystem Memory Chip Select 3 Static Memory Base and Mask registersAd

www.digiembedded.com311System Control ModuleRegister bit assignmentGen ID registerAddress: A090 0210This register is read-only, and indicates the stat

System configuration registers312 NS9750 Hardware ReferenceRegister bit assignmentBits Access Mnemonic Reset DescriptionD31:00 R GENID Reflects the s

www.digiembedded.com313System Control ModuleExternal Interrupt 0–3 Control registerAddress: A090 0214 / 0218 / 021C / 0220The External Interrupt Contr

315Ethernet Communication ModuleCHAPTER 6The Ethernet Communication module consists of an Ethernet Media Access Controller (MAC) and Ethernet front-en

System boot10 NS9750 Hardware ReferenceSystem bootThere are two ways to boot the NS9750 system (see Figure 2): From a fast Flash over the system mem

Overview316 NS9750 Hardware ReferenceOverviewThe Ethernet MAC module provides the following: Station address logic (SAL) Statistics module Interfa

www.digiembedded.com317Ethernet Communication ModuleFigure 63: Ethernet Communication module block diagramEthernet MACThe Ethernet MAC includes a full

Ethernet MAC318 NS9750 Hardware ReferenceFigure 64: Ethernet MAC block diagramFeature DescriptionMAC Core 10/100 megabit Media Access ControllerPerfo

www.digiembedded.com319Ethernet Communication ModuleTable 202 shows how the different PHY interfaces are mapped to the external IO. In addition to the

Ethernet MAC320 NS9750 Hardware ReferenceExternal IO MII RMIIRXD[3] RXD[3] N/CPull low external to NS9750RXD[2] RXD[2] N/CPull low external to NS9750

www.digiembedded.com321Ethernet Communication ModuleStation address logic (SAL)The station address logic module examines the destination address field

Ethernet MAC322 NS9750 Hardware ReferenceIf any of the counters roll over, an associated carry bit is set in the Carry 1 (CAR1) or Carry 2 (CAR2) reg

www.digiembedded.com323Ethernet Communication ModuleEthernet front-end moduleFigure 65 shows the Ethernet front-end module (EFE).Figure 65: Ethernet f

Ethernet front-end module324 NS9750 Hardware Referencememory. Bad frames (for example, invalid checksum or code violation) and frames with unacceptab

www.digiembedded.com325Ethernet Communication Moduleto be received and written into the receive FIFO, but the frame remains in the FIFO until the syst

www.digiembedded.com11About NS9750input reset pin can be driven by a system reset circuit or a simple power-on reset circuit.RESET_DONE as an inputUse

Ethernet front-end module326 NS9750 Hardware Referenceused is read from system memory and stored in the registers internal to the RX_RD logic.Figure

www.digiembedded.com327Ethernet Communication ModuleTransmit packet processorTransmit frames are transferred from system memory to the transmit packet

Ethernet front-end module328 NS9750 Hardware ReferenceI When set, tells the TX_WR logic to set TXBUFC in the Ethernet Interrupt Status register (see

www.digiembedded.com329Ethernet Communication ModuleSetting the EXTDMA (enable transmit DMA) bit in Ethernet General Control Register #1 starts the tr

Ethernet front-end module330 NS9750 Hardware Referencecontain the correct value. In this situation, software must keep track of the location of the n

www.digiembedded.com331Ethernet Communication ModuleThe slave also generates an AHB ERROR if the address is not aligned on a 32-bit boundary, and the

Ethernet front-end module332 NS9750 Hardware ReferenceThe status bits for all interrupts are available in the Ethernet Interrupt Status register, and

www.digiembedded.com333Ethernet Communication ModuleRMIIM MII Management Configuration register10MAC MIIM logicRPERMII PHY Support register 1 0 RMIIBi

External CAM filtering334 NS9750 Hardware ReferenceExternal CAM filteringNS9750 supports external Ethernet CAM filtering, which requires an external

www.digiembedded.com335Ethernet Communication ModuleFigure 68: External Ethernet CAM filtering for MII PHYIn this example, the MII receive interface i

Reset12 NS9750 Hardware ReferenceFigure 3 shows a sample reset circuit.Figure 3: Sample reset circuitYou can use one of five software resets to reset

External CAM filtering336 NS9750 Hardware ReferenceFigure 69: RMII PHY receive interfaceAfter performing the necessary destination address lookup, th

www.digiembedded.com337Ethernet Communication ModuleEthernet Control and Status registersTable 205 shows the address for each Ethernet controller regi

Ethernet Control and Status registers338 NS9750 Hardware ReferenceA060 0448 SA3 Station Address register #3A060 0500 SAFR Station Address Filter regi

www.digiembedded.com339Ethernet Communication ModuleEthernet General Control Register #1Address: A060 0000Register bit assignmentBits Access Mnemonic

Ethernet Control and Status registers340 NS9750 Hardware ReferenceD28 R/W ERXSHT 0 Accept short (<64) receive frames0 Do not accept short frames1

www.digiembedded.com341Ethernet Communication ModuleD19 R/W ERXINIT 0 Enable initialization of RX buffer descriptors0 Do not initialize1 InitializeWhe

Ethernet Control and Status registers342 NS9750 Hardware ReferenceEthernet General Control Register #2Address: A060 0004Register bit assignmentD08 R/

www.digiembedded.com343Ethernet Communication ModuleD03 R/W TCLER 0 Clear transmit error0->1 transition: Clear transmit error.Clears out conditions

Ethernet Control and Status registers344 NS9750 Hardware ReferenceEthernet General Status registerAddress: A060 0008Register bit assignmentEthernet T

www.digiembedded.com345Ethernet Communication ModuleRegister bit assignmentBits Access Mnemonic Reset DescriptionD31:16 N/A Reserved N/A N/AD15 R TXO

www.digiembedded.com13About NS9750Hardware reset duration is 4 ms for PLL to stabilize. Software duration depends on speed grade, as shown in Table 1.

Ethernet Control and Status registers346 NS9750 Hardware ReferenceD10 R TXAEC 0x0 TX abort — excessive collisionsWhen set, indicates that the frame w

www.digiembedded.com347Ethernet Communication ModuleEthernet Receive Status registerAddress: A060 001CThe Ethernet Receive Status register contains th

Ethernet Control and Status registers348 NS9750 Hardware ReferenceMAC Configuration Register #1Address: A060 0400MAC Configuration Register #1 provid

www.digiembedded.com349Ethernet Communication ModuleRegister bit assignmentBits Access Mnemonic Reset DescriptionD31:16 N/A Reserved N/A N/AD15 R/W SR

Ethernet Control and Status registers350 NS9750 Hardware ReferenceD00 R/W RXEN 0 Receive enableSet this bit to 1 to allow the MAC receiver to receive

www.digiembedded.com351Ethernet Communication ModuleMAC Configuration Register #2Address: A060 0404MAC Configuration Register #2 provides additional b

Ethernet Control and Status registers352 NS9750 Hardware ReferenceD08 R/W PUREP 0 Pure preamble enforcement0 No preamble checking is performed1 The M

www.digiembedded.com353Ethernet Communication ModulePAD operation table for transmit framesD02 R/W HUGE 0 Huge frame enable0 Transmit and receive fram

Ethernet Control and Status registers354 NS9750 Hardware ReferenceBack-to-Back Inter-Packet-Gap registerAddress: A060 0408Register bit assignmentBits

www.digiembedded.com355Ethernet Communication ModuleNon Back-to-Back Inter-Packet-Gap registerAddress: A060 040CRegister bit assignmentCollision Windo

System clock14 NS9750 Hardware ReferenceFigure 4: System clockThe PLL parameters are initialized on powerup reset, and can be changed by software fro

Ethernet Control and Status registers356 NS9750 Hardware ReferenceRegister bit assignmentBits Access Mnemonic Reset DescriptionD31:14 N/A Reserved N/

www.digiembedded.com357Ethernet Communication ModuleMaximum Frame registerAddress: A060 0414Register bit assignmentBits Access Mnemonic Reset Descript

Ethernet Control and Status registers358 NS9750 Hardware ReferencePHY Support registerAddress: A060 0418Register bit assignmentBits Access Mnemonic R

www.digiembedded.com359Ethernet Communication ModuleMII Management Configuration registerAddress: A060 0420Register bit assignmentBits Access Mnemonic

Ethernet Control and Status registers360 NS9750 Hardware ReferenceClocks field settingsMII Management Command registerAddress: A060 0424Register bit

www.digiembedded.com361Ethernet Communication ModuleMII Management Address registerAddress: A060 0428Register bit assignmentD01 R/W SCAN 0 Automatical

Ethernet Control and Status registers362 NS9750 Hardware ReferenceMII Management Write Data registerAddress: A060 042CRegister bit assignmentD12:08 R

www.digiembedded.com363Ethernet Communication ModuleMII Management Read Data registerAddress: A060 0430Register bit assignmentMII Management Indicator

Ethernet Control and Status registers364 NS9750 Hardware ReferenceRegister bit assignmentStation Address registersAddress: A060 0440 / 0444 / 0448The

www.digiembedded.com365Ethernet Communication ModuleNote:Octet #6 is the first byte of a frame received from the MAC. Octet #1 is the last byte of the

www.digiembedded.com15About NS9750USB clockUSB is clocked by a separate PLL driven by an external 48 MHz crystal, or it can be driven directly by an e

Ethernet Control and Status registers366 NS9750 Hardware ReferenceStation Address Filter registerAddress: A060 0500The Station Address Filter registe

www.digiembedded.com367Ethernet Communication ModuleHT1 stores enables for the lower 32 CRC addresses; HT2 stores enables for the upper 32 CRC address

Ethernet Control and Status registers368 NS9750 Hardware ReferenceStatistics registersAddress: A060 0680 (base register)The Statistics module has 39

www.digiembedded.com369Ethernet Communication ModuleReceive statistics countersReceive byte counter (A060 069C)Incremented by the byte count of frames

Ethernet Control and Status registers370 NS9750 Hardware ReferenceReceive packet counter (A060 06A0)Incremented for each received frame (including ba

www.digiembedded.com371Ethernet Communication ModuleReceive control frame packet counter (A060 06B0)Incremented for each MAC control frame received (P

Ethernet Control and Status registers372 NS9750 Hardware ReferenceReceive carrier sense error counter (A060 06C8)Incremented each time a false carrie

www.digiembedded.com373Ethernet Communication Moduleincrement when a packet is truncated to 1518 (non-VLAN) or 1522 (VLAN) bytes by MAXF.Transmit stat

Ethernet Control and Status registers374 NS9750 Hardware ReferenceTransmit byte counter (A060 06E0)Incremented by the number of bytes that were put o

www.digiembedded.com375Ethernet Communication ModuleTransmit excessive deferral packet counter (A060 06F8)Incremented for frames aborted because they

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Ethernet Control and Status registers376 NS9750 Hardware ReferenceTransmit total collision packet counter (A060 070C)Incremented by the number of col

www.digiembedded.com377Ethernet Communication ModuleTransmit undersize frame counter (A060 0728)Incremented for every frame less than 64 bytes, with a

Ethernet Control and Status registers378 NS9750 Hardware ReferenceCarry Register 1Address: A060 0730Bits Access Mnemonic Reset DescriptionD31 R/C C16

www.digiembedded.com379Ethernet Communication ModuleCarry Register 2Address: A060 0734D05 R/C C1RCS 0 Carry register 1 RCSE counter carry bitD04 R/C C

Ethernet Control and Status registers380 NS9750 Hardware ReferenceCarry Register 1 Mask registerAddress: A060 0738D10 R/C C2TBC 0 Carry register 2 TB

www.digiembedded.com381Ethernet Communication ModuleD25 R/W M1MGV 1 Mask register 1 TRMGV counter carry bit maskD24:17 N/A Reserved N/A N/AD16 R/W M1R

Ethernet Control and Status registers382 NS9750 Hardware ReferenceCarry Register 2 Mask registerAddress: A060 073CBits Access Mnemonic Reset Descript

www.digiembedded.com383Ethernet Communication ModuleRX_A Buffer Descriptor Pointer registerAddress: A060 0A00Register bit assignmentRX_B Buffer Descri

Ethernet Control and Status registers384 NS9750 Hardware ReferenceRX_C Buffer Descriptor Pointer registerAddress: A060 0A08Register bit assignmentRX_

www.digiembedded.com385Ethernet Communication ModuleEthernet Interrupt Status registerAddress: A060 0A10The Ethernet Interrupt Status register contain

17NS9750 PinoutCHAPTER 2The NS9750 offers a connection to an external bus expansion module, as well as a glueless connection to SDRAM, PC100 DIMM, fla

Ethernet Control and Status registers386 NS9750 Hardware ReferenceD24 R/C RXOVFL_STAT 0 Assigned to RX interrupt.RX status FIFO overflowed.D23 R/C RX

www.digiembedded.com387Ethernet Communication ModuleEthernet Interrupt Enable registerAddress: A060 0A14The Ethernet Interrupt Enable register contain

Ethernet Control and Status registers388 NS9750 Hardware ReferenceRegister bit assignmentBits Access Mnemonic Reset DescriptionD31:26 N/A Reserved N/

www.digiembedded.com389Ethernet Communication ModuleTX Buffer Descriptor Pointer registerAddress: A060 0A18Register bit assignmentTransmit Recover Buf

Ethernet Control and Status registers390 NS9750 Hardware ReferenceRegister bit assignmentTX Error Buffer Descriptor Pointer registerAddress: A060 0A2

www.digiembedded.com391Ethernet Communication ModuleRX_A Buffer Descriptor Pointer Offset registerAddress: A060 0A28D07:00 R TXERBD 0x00 Contains the

Ethernet Control and Status registers392 NS9750 Hardware ReferenceRegister bit assignmentRX_B Buffer Descriptor Pointer Offset registerAddress: A060

www.digiembedded.com393Ethernet Communication ModuleRX_C Buffer Descriptor Pointer Offset registerAddress: A060 0A30Register bit assignmentRX_D Buffer

Ethernet Control and Status registers394 NS9750 Hardware ReferenceRegister bit assignmentTransmit Buffer Descriptor Pointer Offset registerAddress: A

www.digiembedded.com395Ethernet Communication ModuleRX Free Buffer registerAddress: A060 0A3CSo the RX_RD logic knows when the software is freeing a b

Pinout and signal descriptions18 NS9750 Hardware ReferencePinout and signal descriptionsEach pinout table applies to a specific interface, and contai

Ethernet Control and Status registers396 NS9750 Hardware ReferenceTX buffer descriptor RAMAddress: A060 1000The TX buffer descriptor RAM holds 64 tra

www.digiembedded.com397Ethernet Communication ModuleSample hash table codeThis sample C code describes how to calculate hash table entries based on 6-

Sample hash table code398 NS9750 Hardware Reference// create hash table for MAC addresseth_make_hash_table (hash_table);(*MERCURY_EFE) .ht2.bits.data

www.digiembedded.com399Ethernet Communication Module{set_hash_bit ((BYTE *) hash_table, calculate_hash_bit (mca_address[index]));}}/*** Function: void

Sample hash table code400 NS9750 Hardware Reference* Function: int calculate_hash_bit (BYTE *mca)** Description:* This routine calculates which bit i

www.digiembedded.com401Ethernet Communication Modulemcap++;for (bit_index = 0; bit_index < 16; bit_index++){bx = (WORD16) (crc >> 16); /* ge

Sample hash table code402 NS9750 Hardware Reference

403PCI-to-AHB BridgeCHAPTER 7The PCI-to-AHB bridge provides connections between PCI-based modules/devices and the NS9750 AHB bus. Important:This chapt

About the PCI-to-AHB Bridge404 NS9750 Hardware ReferenceAbout the PCI-to-AHB BridgeThe PCI-to-AHB bridge provides these features: Supports PCI speci

www.digiembedded.com405PCI-to-AHB BridgePCI-to-AHB bridge functionalityFigure 71 shows the PCI-to-AHB bridge. Downstream transactions are those initia

www.digiembedded.com19NS9750 PinoutC18 addr[5] 8 O Address bus signalA19 addr[6] 8 O Address bus signalA17 addr[7] 8 O Address bus signalC16 addr[8] 8

About the PCI-to-AHB Bridge406 NS9750 Hardware Referencebeing sent back to the PCI bus. The AHB master interface supports both single and burst trans

www.digiembedded.com407PCI-to-AHB BridgePCI bus arbiterThe PCI bus arbiter (also referred to as PCI arbiter), although embedded in NS9750, is not part

About the PCI-to-AHB Bridge408 NS9750 Hardware ReferenceDETECTED PARITY ERROR bit in the PCI Status register is set. For address parity errors, the S

www.digiembedded.com409PCI-to-AHB Bridgewindow size of each Base Address register is hardwired (see Table 257 on page 417), but each register can be e

About the PCI-to-AHB Bridge410 NS9750 Hardware Reference Bridge receives a target abort (RTA, see "Received target abort" on page 415) Br

www.digiembedded.com411PCI-to-AHB BridgeEndian configurationThe PCI bus is defined as little endian and the AHB bus can be defined as either Big or li

About the PCI-to-AHB Bridge412 NS9750 Hardware ReferenceD23:16 R/W BUS_NUMBER 0x00 Target PCI bus number Bus 0. Considered a local bus, so a Type 0

www.digiembedded.com413PCI-to-AHB BridgeBridge Configuration registersTable 254 shows the standard PCI configuration registers that are supported by t

About the PCI-to-AHB Bridge414 NS9750 Hardware ReferencePCI Vendor ID register Read-only value. To change this value, use the VENDOR_ID field in the

www.digiembedded.com415PCI-to-AHB BridgePCI Status registerTable 256 describes the PCI Status register fields.Bits Access Mnemonic Reset DescriptionD1

Pinout and signal descriptions20 NS9750 Hardware ReferenceH2 clk_en[3] 8 O SDRAM clock enableA10 clk_out[0] 8 O SDRAM reference clock. Connect to clk

About the PCI-to-AHB Bridge416 NS9750 Hardware ReferencePCI Revision ID registerRead-only value. To change this value, use the REVISION_ID field in t

www.digiembedded.com417PCI-to-AHB BridgePCI BIST registerRead-only value, hardwired to 0x0.PCI Base Address registers [5:0]The PCI-to-AHB bridge suppo

PCI bus arbiter418 NS9750 Hardware ReferencePCI Subsystem ID registerRead-only value. To change this value, use the SUBSYSTEM_ID field in the PCI Con

www.digiembedded.com419PCI-to-AHB BridgeNS9750 can be configured to use either the embedded PCI arbiter or an external arbiter through the bootstrap i

PCI bus arbiter420 NS9750 Hardware ReferenceIf there are no new requesters when the current bus master completes its transaction, the bus ownership s

www.digiembedded.com421PCI-to-AHB BridgeAddress Offset Register Description0xA030 0000 PARBCFG PCI Arbiter Configuration0xA030 0004 PARBINT PCI Arbite

PCI bus arbiter422 NS9750 Hardware Reference0xA030 1014–0xA030 1FFC Reserved (all read accesses return 0x0 value)Address Offset Register DescriptionT

www.digiembedded.com423PCI-to-AHB BridgePCI Arbiter Configuration registerAddress: A030 0000The PCI Arbiter Configuration register enables and disable

PCI bus arbiter424 NS9750 Hardware ReferencePCI Arbiter Interrupt Status registerAddress: A030 0004The PCI Arbiter Interrupt Status register reports

www.digiembedded.com425PCI-to-AHB BridgePCI Arbiter Interrupt Enable registerAddress: A030 0008The PCI Arbiter Interrupt Enable register has an enable

www.digiembedded.com21NS9750 PinoutA25 data[21] 8 I/O Data bus signalC22 data[22] 8 I/O Data bus signalD21 data[23] 8 I/O Data bus signalB23 data[24]

PCI bus arbiter426 NS9750 Hardware ReferencePCI Miscellaneous Support registerAddress: A030 000CThe PCI Miscellaneous Support register contains misce

www.digiembedded.com427PCI-to-AHB BridgeRegister bit assignmentBits Access Mnemonic Reset DescriptionD31:10Read only; hard-wired to 0Reserved N/A N/AD

PCI bus arbiter428 NS9750 Hardware ReferencePCI Configuration 0 registerAddress: A030 0010The PCI Configuration 0 register contains the values that w

www.digiembedded.com429PCI-to-AHB BridgeChange these fields only during system initialization, when there is no PCI activity. In a system where NS9750

PCI bus arbiter430 NS9750 Hardware ReferenceRegister bit assignmentPCI Configuration 2 registerAddress: A030 0018The PCI Configuration 2 register con

www.digiembedded.com431PCI-to-AHB BridgeRegister bit assignmentPCI Configuration 3 registerAddress: A030 001CThe PCI Configuration 3 register contains

PCI bus arbiter432 NS9750 Hardware ReferencePCI Bridge Configuration registerAddress: A030 0020The PCI Bridge Configuration register controls the ban

www.digiembedded.com433PCI-to-AHB BridgePCI Bridge AHB Error Address registerAddress: A030 0024The PCI Bridge AHB Error Address register stores the ad

PCI bus arbiter434 NS9750 Hardware ReferenceThe PCI Bridge PCI Error Address register stores the address of the PCI transaction that received a PCI b

www.digiembedded.com435PCI-to-AHB BridgeRegister bit assignmentPCI Bridge Interrupt Enable registerAddress: A030 0030The PCI Bridge Interrupt Enable r

Pinout and signal descriptions22 NS9750 Hardware ReferenceSystem Memory interface signalsTable 4 describes System Memory interface signals in more de

PCI bus arbiter436 NS9750 Hardware ReferenceD13 R/W PRXMAEN 0 PCI received master abort enable0 Interrupt disabled1 Interrupt enabledBit 13 of PCI St

www.digiembedded.com437PCI-to-AHB BridgePCI Bridge AHB to PCI Memory Address Translate 0 registerAddress: A030 0034The PCI Bridge AHB-to-PCI Memory Ad

PCI bus arbiter438 NS9750 Hardware ReferencePCI Bridge AHB to PCI Memory Address Translate 1 registerAddress: A030 0038The PCI Bridge AHB-to-PCI Memo

www.digiembedded.com439PCI-to-AHB BridgePCI Bridge AHB-to-PCI IO Address Translate registerAddress: A030 003CThe PCI Bridge AHB-to-PCI IO Address Tran

PCI bus arbiter440 NS9750 Hardware ReferenceRegister bit assignmentPCI Bridge PCI to AHB Memory Address Translate 1Address: A030 0044The PCI Bridge P

www.digiembedded.com441PCI-to-AHB BridgePCI Bridge Address Translation Control registerAddress: A030 0048The PCI Bridge Address Translation Control re

PCI bus arbiter442 NS9750 Hardware ReferenceCardBus Miscellaneous Support registerAddress: A030 004CThe CardBus Miscellaneous Support register is use

www.digiembedded.com443PCI-to-AHB BridgeD29 R/W CMS_V3_SKT 0 Allows software to control the V3_SKT bit in the CardBus Socket Present State register.Wh

PCI bus arbiter444 NS9750 Hardware ReferenceD21 R/W CMS_DATA_LOST 0 Allows software to control the DATA_LOST bit in the CardBus Socket Present State

www.digiembedded.com445PCI-to-AHB BridgeD15 R/W CMS_CCD1 0 Allows the software to control the CCD1 bit in the Cardbus Socket Present State register. R

www.digiembedded.com23NS9750 Pinoutclk_en[3:0] O SDRAM clock enable. Used for SDRAM devices.Note: The clk_en signals are associated with the dy_cs_n s

PCI bus arbiter446 NS9750 Hardware ReferenceCardBus Socket Event registerAddress: A030 1000The CardBus Socket Event register is used for CardBus appl

www.digiembedded.com447PCI-to-AHB BridgeCardBus Socket Mask registerAddress: A030 1004The CardBus Socket Mask register is used for CardBus application

PCI bus arbiter448 NS9750 Hardware ReferenceRegister bit assignmentCardBus Socket Present State registerAddress: A030 1008The CardBus Socket Present

www.digiembedded.com449PCI-to-AHB BridgeRegister bit assignmentBits Access Mnemonic Reset DescriptionD31 R YV_SKT 0 When set, indicates that VCC=Y.Y v

PCI bus arbiter450 NS9750 Hardware ReferenceD11 R V3_CARD 0 When set, indicates that the card inserted into the socket supports VCC=3.3 volts.This bi

www.digiembedded.com451PCI-to-AHB BridgeCardBus Socket Force Event registerAddress: A030 100CThe CardBus Socket Force Event register is used for CardB

PCI bus arbiter452 NS9750 Hardware ReferenceRegister bit assignmentBits Access Mnemonic Reset DescriptionD31:15 N/A Reserved N/A N/AD14 W CV_TEST N/A

www.digiembedded.com453PCI-to-AHB BridgeD06 N/A Reserved N/A N/AD05 W FCB_CARD N/A Sets the CB_CARD bit in the CardBus Socket Present State register.

PCI bus arbiter454 NS9750 Hardware ReferenceCardBus Socket Control registerAddress: A030 1010The CardBus Socket Control register is used only for Car

www.digiembedded.com455PCI-to-AHB BridgeD02:00 R/W VPP_CTL 000 Socket VPP/Core control000 0 V001 12 V010 5 V011 3.3 V100 Reserved101 Reserved110 1.8 V

Pinout and signal descriptions24 NS9750 Hardware ReferenceFigure 6 shows NS9750 SDRAM clock termination.Figure 6: SDRAM clock terminationC3clk_in[0]c

PCI system configurations456 NS9750 Hardware ReferencePCI system configurationsNS9750 can be connected to the PCI bus using an embedded (internal) or

www.digiembedded.com457PCI-to-AHB BridgeThe internal PCI arbiter is selected when the RTCK pin is set to 1 during powerup. Because the RTCK pad has a

PCI system configurations458 NS9750 Hardware ReferenceDevice selection for configurationThe NS9750 IDSEL pin is used as a chip select during PCI conf

www.digiembedded.com459PCI-to-AHB Bridge AD[31:0], C/BE[3:0], and PAR are driven low when RST# is asserted, to keep the signals from floating.

PCI system configurations460 NS9750 Hardware ReferenceWhen the PCI_CENTRAL_RSC_n pin is pulled high (see Figure 73), these functions operate differen

www.digiembedded.com461PCI-to-AHB BridgeImportant:Note that in cases where NS9750 provides the PCI clock, the PCI clock connection to the NS9750 must

CardBus Support462 NS9750 Hardware ReferenceFigure 74: CardBus system connections to NS9750CONTROLNS9750PCI_CENTRAL_RSC_nPCI CLKINPCI CLKOUTREQ2#REQ3

www.digiembedded.com463PCI-to-AHB BridgeNotes:1The power controller is required only for applications that support hot-insertion and hot-removal of th

CardBus Support464 NS9750 Hardware ReferenceNotes: BOOTSTRAP[1] and PCI_CENTRAL_RSC_n are two strapping pins that must be pulled low to configure th

www.digiembedded.com465PCI-to-AHB Bridge CardBus Socket Event (see "CardBus Socket Event register" on page 446) CardBus Socket Mask (see &

www.digiembedded.com25NS9750 PinoutFigure 7: NS9750 clock enable configurationEthernet interface3.3Vreset_doneclk_en[n]SDRAMNS97500 = B0 TO ANC7SB3157

CardBus Support466 NS9750 Hardware Reference

467BBus BridgeCHAPTER 8The NS9750 ASIC contains two busses that interconnect the peripherals. The high speed peripherals reside on the AMBA AHB bus. T

BBus bridge functions468 NS9750 Hardware ReferenceBBus bridge functionsThe Digi BBus is a low-speed secondary bus that operates at half the AHB clock

www.digiembedded.com469BBus BridgeFigure 75 shows the four functions of the BBus bridge in relation to the AHB bus and the BBus.Figure 75: Basic block

Bridge control logic470 NS9750 Hardware ReferenceFigure 76: BBus bridge block diagramNotes: The AHB bus and BBus clock domains are asynchronous to e

www.digiembedded.com471BBus BridgeDMA accessesThere are two DMA controllers on the NS9750 BBus. One DMA controller services all BBus peripherals excep

BBus control logic472 NS9750 Hardware ReferenceBBus control logicBBus control logic consists of a round-robin arbiter to select a new master, the mul

www.digiembedded.com473BBus BridgeCycles and BBus arbitrationDuring a normal cycle, each bus master cycle is allowed only one read/write cycle if anot

Two-channel AHB DMA controller (AHB bus)474 NS9750 Hardware ReferenceTwo-channel AHB DMA controller (AHB bus)Each DMA channel moves data from the sou

www.digiembedded.com475BBus BridgeWhen the current descriptor is retired, the next descriptor is accessed from a circular buffer. Each DMA buffer desc

ContentsiiiChapter 1: About NS9750 ... 1NS9750 Features .

Pinout and signal descriptions26 NS9750 Hardware ReferenceClock generation/system pinsU3 rxd[1] rxd[1] I Receive data bit 1 Receive data bit 1U2 rxd[

Two-channel AHB DMA controller (AHB bus)476 NS9750 Hardware ReferenceDescriptor list processingWhen a DMA controller has completed the operation spec

www.digiembedded.com477BBus BridgePeripheral DMA read accessFigure 78 and Figure 79 show how the DMA engine performs read accesses of an external peri

Two-channel AHB DMA controller (AHB bus)478 NS9750 Hardware ReferenceFigure 79: Peripheral DMA burst read accessPeripheral DMA write accessFigure 80

www.digiembedded.com479BBus BridgeFigure 81: Peripheral DMA burst write accessPeripheral REQ signalingAn external peripheral indicates that it can acc

Two-channel AHB DMA controller (AHB bus)480 NS9750 Hardware ReferenceDesign LimitationsThe AHB DMA logic contains several design limitations. Careful

www.digiembedded.com481BBus Bridgetransferring data in non-DMA mode do not contribute to the calculation. The worst case AHB DMA response latency occu

Two-channel AHB DMA controller (AHB bus)482 NS9750 Hardware ReferenceStatic RAM chip select configurationThe AHB DMA controller accesses an external

www.digiembedded.com483BBus BridgeInterrupt aggregationAll the peripherals on the BBus, as well as AHB DMA channels 1 and 2 in the BBus bridge, can in

SPI-EEPROM boot logic484 NS9750 Hardware ReferenceSPI-EEPROM boot logicSPI-EEPROM boot logic is enabled by strapping off the boot_cfg pins to the boo

www.digiembedded.com485BBus BridgeCalculation and exampleThis equation calculates the amount of time, in seconds, required to copy the contents of the

www.digiembedded.com27NS9750 PinoutAD20 bist_en_n I Enable internal BIST operationAF21 pll_test_n I Enable PLL testingAE21 scan_en_n I Enable internal

SPI-EEPROM boot logic486 NS9750 Hardware ReferenceMemory Controller configurationNote:See your ARM documentation for complete information about the m

www.digiembedded.com487BBus BridgeSDRAM config All SDRAM components contain a Mode register, which has control information required to successfully ac

SPI-EEPROM boot logic488 NS9750 Hardware ReferenceSDRAM boot algorithmNote:The SDRAM boot logic communicates only with serial channel B.These steps d

www.digiembedded.com489BBus Bridge4 The state machine enters a loop where four NOP words are written to the Fifo Data register and four words are read

BBus Bridge Control and Status registers490 NS9750 Hardware ReferenceBBus Bridge Control and Status registersThe BBus configuration registers are loc

www.digiembedded.com491BBus BridgeBuffer Descriptor Pointer registerAddress: A040 0000 / 0020This register contains a 32-bit pointer to the first buff

BBus Bridge Control and Status registers492 NS9750 Hardware ReferenceRegister bit assignmentBit(s) Access Mnemonic Reset DescriptionD31 R/W CE 0 Chan

www.digiembedded.com493BBus BridgeD24:23 R/W SB 0 Source burst00 101 2 (Recommended for 8-bit devices)10 4 (Recommended for 16-bit devices)11 8 (Recom

BBus Bridge Control and Status registers494 NS9750 Hardware ReferenceDMA Status and Interrupt Enable registerAddress: A040 0008 / 0028The DMA Status

www.digiembedded.com495BBus BridgeRegister bit assignmentBits Access Mnemonic Reset DescriptionD31 RW1TC NCIP 0 Normal completion interrupt pendingSet

Pinout and signal descriptions28 NS9750 Hardware Referencebist_en_n, pll_test_n, and scan_en_nTable 7 is a truth/termination table for bist_en_n, pll

BBus Bridge Control and Status registers496 NS9750 Hardware ReferenceDMA Peripheral Chip Select registerAddress: A040 000C / 002CThe DMA Peripheral C

www.digiembedded.com497BBus BridgeRegister bit assignmentBits Access Mnemonic Reset DescriptionD31:04 R/W Not used 0 Always set to 0.D03 R/W POL 0 Chi

BBus Bridge Control and Status registers498 NS9750 Hardware ReferenceBBus Bridge Interrupt Status registerAddress: A040 1000This register contains th

www.digiembedded.com499BBus BridgeBBus Bridge Interrupt Enable registerAddress: A040 1004The BBus Bridge Interrupt Enable register allows you to enabl

BBus Bridge Control and Status registers500 NS9750 Hardware ReferenceD23:13 R/W Not used 0x000 Always set this field to 0.D12 R/W Not used 0 Always w

501BBus DMA ControllerCHAPTER 9The NS9750 ASIC BBus subsystem contains two DMA controllers, each with 16 channels. Note:These DMA controllers are diff

About the BBus DMA controllers502 NS9750 Hardware ReferenceAbout the BBus DMA controllersThere are two BBus DMA controllers. One DMA controller suppo

www.digiembedded.com503BBus DMA ControllerFigure 83 shows the BBus DMA controller block.Figure 83: DMA controller blockEach DMA controller arbiter det

DMA buffer descriptor504 NS9750 Hardware ReferenceDMA buffer descriptorAll DMA channels operate using a buffer descriptor. Each DMA channel remains i

www.digiembedded.com505BBus DMA ControllerFigure 84: DMA buffer descriptorField DescriptionSource address Identifies the starting location of the sour

www.digiembedded.com29NS9750 PinoutN24 ad[12]1N/A I/O PCI time-multiplexed address/data busN25 ad[13]1N/A I/O PCI time-multiplexed address/data busN26

DMA buffer descriptor506 NS9750 Hardware ReferenceDMA transfer statusThe DMA buffer descriptor status field is updated when the buffer descriptor is

www.digiembedded.com507BBus DMA ControllerBits Mnemonic Description15 MATCH1 Receive character match #114 MATCH2 Receive character match #213 MATCH3 R

DMA buffer descriptor508 NS9750 Hardware ReferenceBits Mnemonic Description15:00 UNUSED Not used — read back 0Table 307: Peripheral bit fields: Seria

www.digiembedded.com509BBus DMA ControllerDMA channel assignmentsEach BBus DMA controller contains 16 DMA channels. Controller DMA1 is dedicated to th

DMA Control and Status registers510 NS9750 Hardware ReferenceDMA Control and Status registersThe configuration registers for DMA1 are located at 0x90

www.digiembedded.com511BBus DMA Controllerwithin each DMA module. The offsets allow address bits [08:05] to encode the DMA channel number.Offset Descr

DMA Control and Status registers512 NS9750 Hardware ReferenceDMA Buffer Descriptor PointerAddress: DMA19000 0130 / 9011 0130 DMA Channel 10 Control r

www.digiembedded.com513BBus DMA Controller9000 0000 / 0020 / 0040 / 0060 / 0080 / 00A0 / 00C0 / 00E0 / 0100 / 0120 / 0140 / 0160 / 0180 / 01A0 / 01C0

DMA Control and Status registers514 NS9750 Hardware ReferenceDMA Control registerAddress: DMA19000 0010 / 0030 / 0050 / 0070 / 0090 / 00B0 / 00D0 / 0

www.digiembedded.com515BBus DMA ControllerD27:26 R/W MODE 0 Fly-by mode00 Fly-by write (peripheral-to-memory)01 Fly-by read (memory-to-peripheral)10 U

Pinout and signal descriptions30 NS9750 Hardware ReferenceY25 idsel3, 4N/A I Initialization device select: For PCI host applications, connect to AD1

DMA Control and Status registers516 NS9750 Hardware ReferenceDMA Status/Interrupt Enable registerAddress: DMA19000 0014 / 0034 / 0054 / 0074 / 0094 /

www.digiembedded.com517BBus DMA ControllerRegister bit assignmentBits Access Mnemonic Reset DescriptionD31 RW1TC NCIP 0 Normal completion interrupt pe

DMA Control and Status registers518 NS9750 Hardware ReferenceD28 RW1TC CAIP 0 Channel abort interrupt pendingSet when the DMA channel finds the CA bi

www.digiembedded.com519BBus DMA Controller

521BBus UtilityCHAPTER 10The BBus utility provides chip-level support for the low speed peripherals in the NS9750 ASIC that reside on the Digi proprie

BBus Utility Control and Status registers522 NS9750 Hardware ReferenceBBus Utility Control and Status registersThe BBus Utility configuration registe

www.digiembedded.com523BBus UtilityMaster Reset registerAddress: 9060 0000The Master Reset register contains the reset control signals for all BBus pe

BBus Utility Control and Status registers524 NS9750 Hardware ReferenceGPIO Configuration registersGPIO Configuration registers #1 – #7 contain the co

www.digiembedded.com525BBus UtilityGPIO Configuration Register #5Address: 9060 0020Bits Access Mnemonic Reset DescriptionD31:28 R/W gpio47 0x3 gpio[47

www.digiembedded.com31NS9750 PinoutPCI/CardBus signalsMost of the CardBus signals are the same as the PCI signals. Other CardBus signals are unique an

BBus Utility Control and Status registers526 NS9750 Hardware ReferenceGPIO Configuration Register #4Address: 9060 001CGPIO Configuration Register #3A

www.digiembedded.com527BBus UtilityGPIO Configuration Register #2Address: 9060 0014Bits Access Mnemonic Reset DescriptionD31:28 R/W gpio23 0x3 gpio[23

BBus Utility Control and Status registers528 NS9750 Hardware ReferenceGPIO Configuration Register #1Address: 9060 0010GPIO Configuration register opt

www.digiembedded.com529BBus UtilityGPIO Control registersGPIO Control Registers #1 and #2 contain the control information for each of the 50 GPIO pins

BBus Utility Control and Status registers530 NS9750 Hardware ReferenceGPIO Control Register #1Address: 9060 0030D15 R/W gpio47 0 gpio[47] control bit

www.digiembedded.com531BBus UtilityBits Access Mnemonic Reset DescriptionD31 R/W gpio31 0 gpio[31] control bitD30 R/W gpio30 0 gpio[30] control bitD29

BBus Utility Control and Status registers532 NS9750 Hardware ReferenceGPIO Status registersGPIO Status Registers #1 and #2 contain the status informa

www.digiembedded.com533BBus UtilityGPIO Status Register #1Address: 9060 0040D16 R gpio48 undefined gpio[48] status bitD15 R gpio47 undefined gpio[47]

BBus Utility Control and Status registers534 NS9750 Hardware ReferenceNote:The reset values for all of the status bits are undefined because they dep

www.digiembedded.com535BBus UtilityBBus Monitor registerAddress: 9060 0050Write 0 to this register.D06 R gpio6 undefined gpio[6] status bitD05 R gpio5

Pinout and signal descriptions32 NS9750 Hardware ReferenceNotes:1 Add external pulldown resistor only if the PCI interface is not being used. See the

BBus Utility Control and Status registers536 NS9750 Hardware ReferenceBBus DMA Interrupt Status registerAddress: 9060 0060The BBus DMA Interrupt Stat

www.digiembedded.com537BBus UtilityBBus DMA Interrupt Enable registerAddress: 9060 0064The BBus DMA Interrupt Enable register allows you to enable or

BBus Utility Control and Status registers538 NS9750 Hardware ReferenceUSB Configuration registerAddress: 9060 0070The USB Configuration register cont

www.digiembedded.com539BBus UtilityEndian Configuration registerAddress: 9060 0080The Endian Configuration register contains the endian control for th

BBus Utility Control and Status registers540 NS9750 Hardware ReferenceRegister bit assignmentBits Access Mnemonic Reset DescriptionD31:13 R Not used

www.digiembedded.com541BBus UtilityARM Wake-up registerAddress: 9060 0090The ARM Wake-up register contains the ARM wake-up word used only by Serial Co

543I2C Master/Slave InterfaceCHAPTER 11The I2C master/slave interface provides an interface between the ARM CPU and the I2C bus. The I2C master/slave

Overview544 NS9750 Hardware ReferenceOverviewThe I2C module is designed to be a master and slave. The slave is active only when the module is being a

www.digiembedded.com545I2C Master/Slave InterfaceI2C external addressesI2C external [bus] addresses are allocated as two groups of eight addresses (00

www.digiembedded.com33NS9750 PinoutFigure 8: NS9750 unused PCI terminationR6 10KPCI_CLKOUTR2 10K3.3VPCI_CLKINDEVSEL-IRDY-PERR-STOP-R7 10KFRAME-R8 10KR

I2C command interface546 NS9750 Hardware ReferenceLocked interrupt driven modeI2C operates in a locked interrupt driven mode, which means that each c

www.digiembedded.com547I2C Master/Slave InterfaceBus arbitrationAny M_READ or M_WRITE command causes the I2C module to participate in the bus arbitrat

I2C registers548 NS9750 Hardware ReferenceCommand Transmit Data registerAddress: 9050 0000The Command Transmit Data (CMD_TX_DATA_REG) register is the

www.digiembedded.com549I2C Master/Slave InterfaceStatus Receive Data registerAddress: 9050 0000The Status Receive Data register (STATUS_RX_DATA_REG) i

I2C registers550 NS9750 Hardware ReferenceMaster Address registerAddress: 9050 0004If using 7-bit addressing, the master device address field uses on

www.digiembedded.com551I2C Master/Slave InterfaceSlave Address registerAddress: 9050 0008If using 7-bit addressing, the slave device address field use

I2C registers552 NS9750 Hardware ReferenceConfiguration registerAddress: 9050 000CThe Configuration register controls the timing on the I2C bus. This

www.digiembedded.com553I2C Master/Slave InterfaceInterrupt CodesInterrupts are signaled in the irq_code field in the STATUS_REG, by providing the appr

Interrupt Codes554 NS9750 Hardware Reference2hexM_NO_ACK Master No acknowledge by slave3hexM_TX_DATA Master TX data required in register TX_DATA4hexM

www.digiembedded.com555I2C Master/Slave InterfaceSoftware driverThe I2C master software driver uses three commands only: M_READ to start a read seque

Pinout and signal descriptions34 NS9750 Hardware ReferenceGPIO MUX The BBus utility contains the control pins for each GPIO MUX bit. Each pin can be

Flow charts556 NS9750 Hardware ReferenceFlow chartsMaster module (normal mode, 16-bit)host idlewrite (optional)M_ADDR_REGwrite cmdM_READwait irqreadr

www.digiembedded.com557I2C Master/Slave InterfaceNotes:1 Writing M_ADDR_REQ is not required if the device address is not changed.2 Read on a non-exist

559LCD ControllerCHAPTER 12The NS9750 LCD (Liquid Crystal Display) controller is a DMA master module that connects to the AHB bus. The LCD controller

LCD features560 NS9750 Hardware ReferenceLCD featuresThe NS9750 LCD controller provides these features: Dual 64-deep, 32-bit wide FIFOs, for bufferi

www.digiembedded.com561LCD Controller Signal polarity, active high or low AC panel bias Panel clock frequency Bits-per-pixel Display type, STN mo

LCD features562 NS9750 Hardware ReferenceNumber of colorsThe number of colors supported differs per panel type.TFT panelsTFT panels support one or mo

www.digiembedded.com563LCD ControllerMono STN panelsMono STN panels support one or more of these modes: 1 bpp, palettized, 2 grayscales selected from

LCD controller functional overview564 NS9750 Hardware ReferenceFigure 85: Power up and power down sequencesLCD controller functional overviewThe LCD

www.digiembedded.com565LCD ControllerDepending on the LCD type and mode, the unpacked data can represent one of the following: An actual true display

www.digiembedded.com35NS9750 PinoutAE17 gpio[4]1U 2 I/O 00 Ser port B DTR01 1284 busy (peripheral-driven)02 DMA ch 1 done03 GPIO 4AF17 gpio[5] U 2 I/O

LCD controller functional overview566 NS9750 Hardware ReferenceSignals and interruptsThe LCD controller provides a set of programmable display contro

www.digiembedded.com567LCD ControllerFigure 86: LCD controller block diagramAHB slave interface Timing controllerPanel clockgeneratorAHB masterinterfa

AHB interface568 NS9750 Hardware ReferenceAHB interfaceThe AHB interface includes the AHB slave interface and the AHB master interface.AHB master and

www.digiembedded.com569LCD ControllerPixel serializerThe pixel serializer block reads the 32-bit wide LCD data from DMA FIFO output port, and extracts

AHB interface570 NS9750 Hardware ReferenceFigure 87: LBLP, DMA FIFO output bits 31:16Figure 88: LBLP, DMA FIFO output bits 15:0DMA FIFO OUTPUT BITSbp

www.digiembedded.com571LCD ControllerFigure 89: BBBP, DMA FIFO output bits 31:16Figure 90: BBBP, DMA FIFO output bits 15:0DMA FIFO OUTPUT BITSbpp12481

AHB interface572 NS9750 Hardware ReferenceFigure 91: LBBP, DMA FIFO output bits 31:16Figure 92: LBBP, DMA FIFO output bits 15:0DMA FIFO OUTPUT BITSbp

www.digiembedded.com573LCD ControllerRAM paletteThe palette RAM is a 256 x 16 bit dual port RAM, physically structured as 128 x 32 bit. This allows tw

AHB interface574 NS9750 Hardware ReferenceIn 16- and 24-bpp TFT mode, the palette is bypassed and the pixel serializer output is used as the TFT pane

www.digiembedded.com575LCD ControllerGenerating interruptsThe LCD controller has three individually masked interrupts and a single combined interrupt.

iv Chapter 3: Working with the CPU ...47About the processor...

Pinout and signal descriptions36 NS9750 Hardware ReferenceAE14 gpio[12]1U 2 I/O 00 Ser port A DTR01 Reserved02 Reserved03 GPIO 12AF14 gpio[13] U 2 I/

AHB interface576 NS9750 Hardware ReferenceTable 346 shows which CLD[23:0] pins provide the pixel data to the STN panel for each mode of operation. Th

www.digiembedded.com577LCD ControllerTable 347 shows which CLD[23:0] pins are used to provide the pixel data to the TFT panel for each mode of operati

AHB interface578 NS9750 Hardware ReferenceThis LCD TFT panel signal multiplexing table shows the RGB alignment to a 15-bit TFT with the intensity bit

www.digiembedded.com579LCD ControllerIf you want reduced resolution, the least significant color bits can be dropped, starting with Red[0], Green[0],

Registers580 NS9750 Hardware ReferenceLCDTiming0Address: A080 0000The LCDTiming0 register controls the horizontal axis panel, which includes: Horizo

www.digiembedded.com581LCD ControllerHorizontal timing restrictionsDMA requests new data at the beginning of a horizontal display line. Some time must

Registers582 NS9750 Hardware ReferenceLCDTiming1Address: A080 0004The LCDTiming1 register controls the vertical axis panel, which includes: Number o

www.digiembedded.com583LCD ControllerLCDTiming2 registerAddress: A080 0008The LCDTiming2 register provides controls for the timing signals.D23:16 R/W

Registers584 NS9750 Hardware ReferenceRegister bit assignmentBits Access Mnemonic Reset DescriptionD31:27 N/A Reserved N/A N/AD26 R/W BCD 0x0 Bypass

www.digiembedded.com585LCD ControllerD13 R/W IPC 0x0 Invert panel clock0 Data changes on the rising edge of CLCP.1 Data changes on the falling edge of

www.digiembedded.com37NS9750 PinoutAC12 gpio[20]1U 8 I/O 00 Ser port C DTR01 LCD clock02 Reserved03 GPIO 20AF11 gpio[21] U 4 I/O 00 Ser port C DSR01 L

Registers586 NS9750 Hardware ReferencePanel clock divider restrictionsThe data path latency forces some restrictions on the usable minimum values for

www.digiembedded.com587LCD ControllerLCDTiming3Address: A080 000CLCDTiming3 controls whether the line-end signal, CLLE, is enabled. When enabled, a po

Registers588 NS9750 Hardware ReferenceLCDUPBASE is used for these displays: TFT Single panel STN Upper panel of dual panel STNLCDLPBASE is used fo

www.digiembedded.com589LCD ControllerRegister bit assignmentLCDINTRENABLEAddress: A080 0018LCDINTRENABLE is the interrupt enable register. Setting bit

Registers590 NS9750 Hardware ReferenceRegister bit assignmentLCDControl registerAddress: A080 001CThe LCDControl register controls the mode in which

www.digiembedded.com591LCD ControllerD16 R/W WATERMARK 0x0 LCD DMA FIFO watermark level0 LCD controller requests AHB bus when either of the DMA FIFOs

Registers592 NS9750 Hardware ReferenceD07 R/W LcdDual 0x0 LCD interface is dual panel STN0 Single panel LCD is in use.1 Dual panel LCD is in use.D06

www.digiembedded.com593LCD ControllerLCDStatus registerAddress: A080 0020The LCDStatus register provides raw interrupt status. On a read, the registe

Registers594 NS9750 Hardware ReferenceLCDInterrupt registerAddress: A080 0024The LCDInterrupt register is a bit-by-bit logical AND of the LCDStatus r

www.digiembedded.com595LCD ControllerRegister bit assignmentRegister bit assignmentLCDPalette registerAddress A080 0200 – 03FCLCDPalette registers con

Pinout and signal descriptions38 NS9750 Hardware ReferenceAE9 gpio[28] U 4 I/O 00 Ext IRQ 1 (duplicate)01 LCD data bit 402 LDC data bit 8 (duplicate)

Registers596 NS9750 Hardware ReferenceEach word location contains two palette entries, which means that 128 word locations are used for the palette.

www.digiembedded.com597LCD ControllerD20:16 R/W R[4:0] N/A Red palette data For STN color displays, only the four most significant bits (04:01) are u

Interrupts598 NS9750 Hardware ReferenceInterruptsThe LCD controller drives a single interrupt back to the system, from four interrupt sources. Each o

www.digiembedded.com599LCD ControllerLBUINTR — Next base address update interruptThe LCD next base address update interrupt is asserted when either th

Interrupts600 NS9750 Hardware Reference

601Serial Control Module: UART CHAPTER 13The NS9750 ASIC supports four independent universal asynchronous/synchronous receiver/transmitter channels. E

Features602 NS9750 Hardware ReferenceFeaturesEach channel supports these features: DMA transfers to and from system memory Independent programmable

www.digiembedded.com603Serial Control Module: UARTFigure 93 shows the structure of the serial module.Figure 93: Serial Module structureBit-rate genera

UART mode604 NS9750 Hardware ReferenceUART modeMany applications require a simple mechanism for sending low-speed information between two pieces of e

www.digiembedded.com605Serial Control Module: UARTreceiver waits for the start bit. When it finds the high-to-low transition, the receiver counts 8 sa

www.digiembedded.com39NS9750 PinoutAF5 gpio[36] U 4 I/O 00 Reserved01 1284 Data 5 (bidirectional)02 LCD data bit 1203 GPIO 36AD6 gpio[37] U 4 I/O 00 R

FIFO management606 NS9750 Hardware Reference When the system is configured to operate in little endian mode, the least significant bytes in the word

www.digiembedded.com607Serial Control Module: UART When the system is configured to operate in little endian mode, the least significant bytes in the

Serial port performance608 NS9750 Hardware ReferenceTo facilitate an interrupt when either the RRDY or RBC status bits are active, the processor must

www.digiembedded.com609Serial Control Module: UART9020 0008 Channel B Status Register A9020 000C Channel B Bit-Rate register9020 0010 Channel B FIFO D

Serial port control and status registers610 NS9750 Hardware ReferenceThe configuration registers for serial controller C are located at 0x9030_0000;

www.digiembedded.com611Serial Control Module: UARTSerial Channel B/A/C/D Control Register AAddress: 9020 0000 / 00409030 0000 / 0040There are two Seri

Serial port control and status registers612 NS9750 Hardware ReferenceD28 R/W EPS 0 Even parity select0 Odd parity1 Even parityDetermines whether the

www.digiembedded.com613Serial Control Module: UARTD21 R/W RL 0 Remote loopbackProvides a remote loopback feature. When RL is set to 1, the TXD transmi

Serial port control and status registers614 NS9750 Hardware ReferenceSerial Channel B/A/C/D Control Register BAddress: 9020 0004 / 00449030 0004 / 00

www.digiembedded.com615Serial Control Module: UARTReserved Reserved13121110987654321015 1431 29 28 27 26 25 24 23 22 21 20 19 18 17 1630RCGTRBGT MODE

Pinout and signal descriptions40 NS9750 Hardware ReferenceAD2 gpio[44]1U 4 I/O 00 Ser port D TxData / SPI port D dout01 1284 Select (peripheral-drive

Serial port control and status registers616 NS9750 Hardware ReferenceRegister bit assignmentBits Access Mnemonic Reset DescriptionD31:28 R/W RDM 0x0

www.digiembedded.com617Serial Control Module: UARTSerial Channel B/A/C/D Status Register AAddress: 9020 0008 / 00489030 0008 / 0048The fields in Seria

Serial port control and status registers618 NS9750 Hardware ReferenceBits Access Mnemonic Reset DescriptionD31:28 R MATCH 0x0 Match bit[31] Match1[30

www.digiembedded.com619Serial Control Module: UARTD26 R CGAP 0 Character GAP timerSet when the enable receive character GAP timer is set in Serial Cha

Serial port control and status registers620 NS9750 Hardware ReferenceD17 R DSR 0 Data set ready0 Inactive1 ActiveIndicates the current state of the E

www.digiembedded.com621Serial Control Module: UARTD12 R ROVER 0 Receive overrunIndicates that a receive overrun error condition has been found. An ove

Serial port control and status registers622 NS9750 Hardware ReferenceD10 R RHALF 0 Receive FIFO half fullIndicates that the receive data FIFO contain

www.digiembedded.com623Serial Control Module: UARTD05 R DSRI 0 Change in DSRIndicates a state change in the EIA data set ready signal.A 1 indicates th

Serial port control and status registers624 NS9750 Hardware ReferenceSerial Channel B/A/C/D Bit-rate registerAddress: 9020 000C / 004C9030 000C / 004

www.digiembedded.com625Serial Control Module: UARTD28 R/W TXSRC 0 Transmit clock source0 Internal1 External (input using GPIO pin)Controls the source

www.digiembedded.com41NS9750 PinoutExample: Implementing gpio[16] and gpio[17]2 gpio[17] is used as both a bootstrap input pin for PLL_ND and an outpu

Serial port control and status registers626 NS9750 Hardware ReferenceD25:24 R/W CLKMUX 00 Bit-rate generator clock sourceControls the bit-rate genera

www.digiembedded.com627Serial Control Module: UARTThe next tables show sample UART baud rates. These rates can be produced using the recommended PLL r

Serial port control and status registers628 NS9750 Hardware ReferenceBaud rateN fieldx8 UART mode x16 UART mode x32 UART mode75 N/A 12287 6143150 122

www.digiembedded.com629Serial Control Module: UARTSerial Channel B/A/C/D FIFO Data registerAddress: 9020 0010 / 00509030 0010 / 0050The Serial Channel

Serial port control and status registers630 NS9750 Hardware ReferenceReading from the receive register empties the receive FIFO. Data is available wh

www.digiembedded.com631Serial Control Module: UARTRegister bit assignmentBits Access Mnemonic Reset DescriptionD31 R/W TRUN 0 Buffer GAP timer enable0

Serial port control and status registers632 NS9750 Hardware ReferenceSerial Channel B/A/C/D Receive Character GAP TimerAddress: 9020 0018 / 00589030

www.digiembedded.com633Serial Control Module: UARTD19:00 CT CT0x00000Character GAP timerDefines the required value for the receive character GAP timer

Serial port control and status registers634 NS9750 Hardware ReferenceSerial Channel B/A/C/D Receive Match registerAddress: 9020 001C / 005C9030 001C

www.digiembedded.com635Serial Control Module: UARTSerial Channel B/A/C/D Receive Match MASK registerAddress: 9020 0020 / 00609030 0020 / 0060The Seria

Pinout and signal descriptions42 NS9750 Hardware ReferenceLCD module signalsThe LCD module signals are multiplexed with GPIO pins. They include seven

Serial port control and status registers636 NS9750 Hardware ReferenceSerial Channel B/A/C/D Flow Control registerAddress: 9020 0034 / 00749030 0034 /

www.digiembedded.com637Serial Control Module: UARTD05:04 R/W FLOW3 10 Flow control enable00 Disabled01 Disabled10 Change field FLOW_STATE to XON upon

Serial port control and status registers638 NS9750 Hardware ReferenceSerial Channel B/A/C/D Flow Control Force registerAddress: 9020 0038 / 00789030

www.digiembedded.com639Serial Control Module: UARTD16 R/W FORCE_EN 0 Force transmitAllows you to force the transmitter to send the character specified

Serial port control and status registers640 NS9750 Hardware Reference

www.digiembedded.com641Serial Control Module: UART

643Serial Control Module: SPI CHAPTER 14The NS9750 ASIC supports four independent universal asynchronous/synchronous receiver/transmitter channels. Ea

Features644 NS9750 Hardware ReferenceFeaturesEach channel supports these features: DMA transfers to and from system memory Independent programmable

www.digiembedded.com645Serial Control Module: SPIBit-rate generatorEach serial channel supports an independent programmable bit-rate generator. The bi

www.digiembedded.com43NS9750 PinoutI2C interfaceUSB interfaceNotes: If not using the USB interface, these pins should be pulled down to ground throug

SPI mode646 NS9750 Hardware ReferenceSPI modeThe NS9750 ASIC SPI controller provides these key features: Four-wire interface (DATA_OUT, DATA_IN, CLK

www.digiembedded.com647Serial Control Module: SPIFIFO managementData flow between a serial controller and memory occurs through the FIFO blocks within

FIFO management648 NS9750 Hardware ReferenceProcessor interrupts vs. DMAThe transmit FIFO can be filled using processor interrupts or the DMA control

www.digiembedded.com649Serial Control Module: SPIWhen reading from the receive FIFO, the processor must perform a long word read operation. Each time

Serial port performance650 NS9750 Hardware ReferenceUsing the DMA controllerWhen using DMA, the processor need not interface with any of the serial p

www.digiembedded.com651Serial Control Module: SPIThe configuration registers for serial controller C are located at 0x9030_0000; the configuration reg

Serial port control and status registers652 NS9750 Hardware ReferenceSerial Channel B/A/C/D Control Register AAddress: 9020 0000 / 00409030 0000 / 00

www.digiembedded.com653Serial Control Module: SPID20 R/W LL 0 Local loopbackProvides an internal local loopback feature. When LL is set to 1, the inte

Serial port control and status registers654 NS9750 Hardware ReferenceD00 R/W ETXDMA 0 Enable transmit DMAEnables the transmitter to interact with a D

www.digiembedded.com655Serial Control Module: SPISerial Channel B/A/C/D Control Register BAddress: 9020 0004 / 00449030 0004 / 0044There are two Seria

Pinout and signal descriptions44 NS9750 Hardware ReferenceFigure 9: JTAG interfaceAE19 tdo 2 O Test data outAC18 tms U I Test mode selectAF20 trst_n

Serial port control and status registers656 NS9750 Hardware ReferenceD21:20 R/W MODE 00 Serial channel mode00 UART mode01 Reserved10 SPI master mode1

www.digiembedded.com657Serial Control Module: SPISerial Channel B/A/C/D Status Register AAddress: 9020 0008 / 00489030 0008 / 0048The fields in Serial

Serial port control and status registers658 NS9750 Hardware ReferenceD12 R ROVER 0 Receive overrunIndicates that a receive overrun error condition ha

www.digiembedded.com659Serial Control Module: SPID10 R RHALF 0 Receive FIFO half fullIndicates that the receive data FIFO contains at least 20 bytes (

Serial port control and status registers660 NS9750 Hardware ReferenceSerial Channel B/A/C/D Bit-rate registerAddress: 9020 000C / 004C9030 000C / 004

www.digiembedded.com661Serial Control Module: SPIRegister bit assignmentBits Access Mnemonic Reset DescriptionD31 R/W EBIT 0 Bit-rate generator enable

Serial port control and status registers662 NS9750 Hardware ReferenceD26 R/W TXEXT 0 Drive transmit clock external0 Disable1 EnableEnables the transm

www.digiembedded.com663Serial Control Module: SPID22 R/W RXCINV 0 Receive clock invertControls the relationship between receive clock and receive data

Serial port control and status registers664 NS9750 Hardware ReferenceD18:17 R/W RDCR 00 Receive clock divide rate00 1x clock mode (only NRZ or NRZI a

www.digiembedded.com665Serial Control Module: SPISerial Channel B/A/C/D FIFO Data registerAddress: 9020 0010 / 00509030 0010 / 0050The Serial Channel

www.digiembedded.com45NS9750 PinoutReservedPin# DescriptionJ1 Tie to ground directlyK3 Tie to ground directlyK2 Tie to ground directlyK1 Tie to ground

Serial port control and status registers666 NS9750 Hardware Referencethe Serial Channel FIFO Data register automatically clears the RRDY bit in Seria

www.digiembedded.com667Serial Control Module: SPI

669IEEE 1284 Peripheral ControllerCHAPTER 15The IEEE 1284 peripheral port supports compatibility mode, nibble mode, byte mode, and ECP mode of operati

Requirements670 NS9750 Hardware ReferenceRequirementsTwo components are required to run the IEEE 1284 peripheral-to-host interface: Clock divider. R

www.digiembedded.com671IEEE 1284 Peripheral ControllerNote:Traffic direction in the IEEE 1284 is classified as either forward or reverse. The forward

Overview672 NS9750 Hardware ReferenceNibble modeNibble mode can send a byte of information to the host by sending two nibbles. This mode operates onl

www.digiembedded.com673IEEE 1284 Peripheral ControllerECP modeECP (extended capability port) mode provides a high performance bi-directional communica

Overview674 NS9750 Hardware ReferenceFigure 99: ECP mode forward transfer cyclesX Host processing sequence example:1 The host puts the data on the da

www.digiembedded.com675IEEE 1284 Peripheral ControllerFigure 100: ECP reverse channel transfer cyclesData and command FIFOsSeparate data and command F

vTLB structure...104Caches and write buffer...

Pinout and signal descriptions46 NS9750 Hardware ReferencePower groundPin # Signal name DescriptionJ23, L23, K23, U23, T23, V23, D18, D17, AC17, D16,

Overview676 NS9750 Hardware ReferenceBecause the NS9750 functions only as a slave, it is not necessary to provide the capability of driving any non-I

www.digiembedded.com677IEEE 1284 Peripheral ControllerThe NS9750 directly supports RLE compression. The device ID can be returned in any supported rev

BBus slave and DMA interface678 NS9750 Hardware Reference9040 0008 FIFO Status FIFO Status register9040 000C FwdCmdFifoReadReg Forward Command FIFO R

www.digiembedded.com679IEEE 1284 Peripheral ControllerIEEE 1284 General Configuration registerAddress: 9040 0000The IEEE 1284 General Configuration re

BBus slave and DMA interface680 NS9750 Hardware ReferenceD13 R/W CPS 0x0 Connector PLH signal0 Indicates to the host that this interface is not ready

www.digiembedded.com681IEEE 1284 Peripheral ControllerInterrupt Status and Control registerAddress: 9040 0004The Interrupt Status and Control register

BBus slave and DMA interface682 NS9750 Hardware ReferenceD23 R/W FDBGM 0x0 Forward data FIFO byte gap mask (FwDatFifoByteGapMask)0 Mask the interrupt

www.digiembedded.com683IEEE 1284 Peripheral ControllerD07 R/C FDFBG 0x0 Forward data FIFO byte gap(FwDatFifoByteGap)The forward data byte gap timer ex

BBus slave and DMA interface684 NS9750 Hardware ReferenceFIFO Status registerAddress: 9040 0008The FIFO Status register allows the CPU to determine t

www.digiembedded.com685IEEE 1284 Peripheral ControllerD11 R FCFR 0x0 Forward command FIFO ready(FwCmdFifoReady)Asserted if forward command in FIFO is

47Working with the CPUCHAPTER 3The NS9750 core is based on the ARM926EJ-S processor. The ARM926EJ-S processor belongs to the ARM9 family of general-pu

BBus slave and DMA interface686 NS9750 Hardware ReferenceForward Command FIFO Read registerAddress: 9040 000CRegister bit assignmentD01 R RFAF 0x0 Re

www.digiembedded.com687IEEE 1284 Peripheral ControllerForward Data FIFO Read registerAddress: 9040 0010Register bit assignmentReverse FIFO Write regis

BBus slave and DMA interface688 NS9750 Hardware ReferenceRegister bit assignmentBits Access Mnemonic Reset DescriptionD31:00 W RvFifoWriteReg N/A Wri

www.digiembedded.com689IEEE 1284 Peripheral ControllerForward Command DMA Control registerAddress: 9040 0024The Forward Command DMA Control register c

BBus slave and DMA interface690 NS9750 Hardware ReferenceRegister bit assignmentForward Data DMA Control registerAddress: 9040 0028The Forward Data D

www.digiembedded.com691IEEE 1284 Peripheral Controllerb Forward data FIFO ready, which normally means the threshold has been met, is asserted. This re

BBus slave and DMA interface692 NS9750 Hardware ReferenceRegister bit assignmentPort Status register, hostAddress: 9040 0104Register bit assignmentBi

www.digiembedded.com693IEEE 1284 Peripheral ControllerPort Control registerAddress: 9040 0108Note:The Port Control register can control IEEE 1284 pins

BBus slave and DMA interface694 NS9750 Hardware ReferencePort Status register, peripheralAddress: 9040 010CFeature Control Register AAddress: 9040 01

www.digiembedded.com695IEEE 1284 Peripheral ControllerRegister bit assignmentFeature Control Register BAddress: 9040 0118You must set bit[0] to 1 in F

About the processor48 NS9750 Hardware ReferenceAbout the processorThe ARM926EJ-S processor supports the 32-bit ARM and 16-bit Thumb instructions sets

BBus slave and DMA interface696 NS9750 Hardware ReferenceD05 R/W PinSelectInterrupt 0x0 Pin select interrupt enable0 Disable1 EnableD04 R/W ECPChanne

www.digiembedded.com697IEEE 1284 Peripheral ControllerMaster Enable registerAddress: 9040 0120The Master Enable register enables different IEEE 1284 m

BBus slave and DMA interface698 NS9750 Hardware ReferenceExtensibility Byte Requested by HostAddress: 9040 0124This register is updated shortly after

www.digiembedded.com699IEEE 1284 Peripheral ControllerRegister bit assignmentInterrupt Status registerAddress: 9040 012CInterrupts are cleared when th

BBus slave and DMA interface700 NS9750 Hardware ReferencePin Interrupt Mask registerAddress: 9040 0134The Pin Interrupt Mask register enables IEEE 12

www.digiembedded.com701IEEE 1284 Peripheral ControllerPin Interrupt Control registerAddress: 9040 0138The Pin Interrupt Control register configures IE

BBus slave and DMA interface702 NS9750 Hardware ReferenceGranularity Count registerAddress: 9040 0168The Granularity Count register controls the valu

www.digiembedded.com703IEEE 1284 Peripheral ControllerForward Address registerAddress: 9040 0174The Forward Address register is updated when a channel

BBus slave and DMA interface704 NS9750 Hardware ReferenceCore Phase (IEEE1284) registerAddress: 9040 0178Register bit assignmentBits Access Mnemonic

www.digiembedded.com705IEEE 1284 Peripheral ControllerWarning:The NS9750 cannot proceed to the Host Busy Data Available protocol state directly from n

www.digiembedded.com49Working with the CPUFigure 10 shows the main blocks in the ARM926EJ-S processor.Figure 10: ARM926EJ-S processor block diagramIns

707USB Controller ModuleCHAPTER 16USB 2.0 provides a standard “plug-and-play” interface for desktop communications at low to moderate speeds. The USB

Overview708 NS9750 Hardware ReferenceOverviewUSB consists of point-to-point connections between one host and any number of hubs and devices; the numb

www.digiembedded.com709USB Controller ModuleFigure 101: USB module architectureThe device block handles most packets that contain control and/or confi

USB device block710 NS9750 Hardware Referencegiven pipe has not been configured or updated, or otherwise is not ready to send or receive the required

www.digiembedded.com711USB Controller ModulePacket and data flowThe device block responds to packets initiated by the host. There are 16 DMA channels

Host block712 NS9750 Hardware ReferenceLogical and physical endpointsEach alternate of each interface of each configuration can use as many as 16 log

www.digiembedded.com713USB Controller ModuleFigure 103: USB host architecturePacket data flowThe host block initiates all transfers on the USB. Data t

USB device endpoint714 NS9750 Hardware Referenceconsumed. Burst transfers move a maximum of 8 bytes in long word transactions. FIFO content from more

www.digiembedded.com715USB Controller ModuleHandling USB-IN packet errorsUSB-IN packet errors are sent from the USB device to the USB host. The USB ho

Instruction sets50 NS9750 Hardware ReferenceARM instruction setThe ARM instruction set allows a program to achieve maximum performance with the minim

USB block registers716 NS9750 Hardware ReferenceUSB block registersThe USB module configuration registers are located at base address 9010_0000. Tabl

www.digiembedded.com717USB Controller ModuleGlobal Control and Status registerAddress: 9010 0000The Global Control and Status register contains all US

USB Global registers718 NS9750 Hardware ReferenceDevice Control and Status registerAddress: 9010 0004The Device Control and Status register contains

www.digiembedded.com719USB Controller ModuleRegister bit assignmentBits Access Mnemonic Reset DescriptionD31 R/W RESUME(RSME)0 ResumeSet to 1 by the d

USB Global registers720 NS9750 Hardware ReferenceGlobal Interrupt Enable registerAddress: 9010 000CThe Global Interrupt Enable register contains the

www.digiembedded.com721USB Controller ModuleGlobal Interrupt Status registerAddress: 9010 0010The Global Interrupt Status register contains the global

USB Global registers722 NS9750 Hardware ReferenceFor diagnostics, each bit serviced here can also be set to 1 by writing a 1 when the bit is set to 0

www.digiembedded.com723USB Controller ModuleD19 R DMA6 0 DMA channel 6 interrupt. Service in the USB DMA block.D18 R DMA5 0 DMA channel 5 interrupt.

USB Global registers724 NS9750 Hardware ReferenceDevice IP Programming Control/Status registerAddress: 9010 0014The Device IP Programming Control/Sta

www.digiembedded.com725USB Controller ModuleUSB host block registersThe USB Host Block registers are for the host controller defined in the Open HCI s

www.digiembedded.com51Working with the CPUSystem control processor (CP15) registersThe system control processor (CP15) registers configure and control

USB host block registers726 NS9750 Hardware ReferenceHCRevision registerAddress: 9010 10009010 1008 HcCommandStatus register9010 100C HcInterrupt Sta

www.digiembedded.com727USB Controller ModuleRegister bit assignmentHcControl registerAddress: 9010 1004The HcControl register defines the operating mo

USB host block registers728 NS9750 Hardware ReferenceD10 R/W RWE 0b RemoteWakeupEnableEnables or disables the remote wakeup feature when upstream res

www.digiembedded.com729USB Controller ModuleD07:06 R/W HCFS 00b HostControllerFunctionalState(b = binary)00bUSBRESET (initial state)01bUSBRESUME10b US

USB host block registers730 NS9750 Hardware ReferenceHcCommandStatus registerAddress: 9010 1008D03 R/W IE 0b IsochronousEnableEnables/disables proces

www.digiembedded.com731USB Controller ModuleThe host controller uses the HcCommandStatus register to receive commands issued by the host controller dr

USB host block registers732 NS9750 Hardware ReferenceD15:04 N/A Reserved N/A N/AD03 R/W OCR 0b OwnershipChangeRequestSet by an OS host controller to

www.digiembedded.com733USB Controller ModuleHcInterruptStatus registerAddress: 9010 100CThe HcInterruptStatus register provides status on various even

USB host block registers734 NS9750 Hardware ReferenceRegister bit assignmentBits Access Mnemonic Reset DescriptionD31 N/A Reserved N/A N/AD30 R/W OC

www.digiembedded.com735USB Controller ModuleHcInterruptEnable registerAddress: 9010 1010Each enable bit in the HcInterruptEnable register corresponds

System control processor (CP15) registers52 NS9750 Hardware ReferenceAccessing CP15 registersUse only MRC and MCR instructions, only in privileged mo

USB host block registers736 NS9750 Hardware ReferenceRegister bit assignmentBits Access Mnemonic Reset DescriptionD31 R/W MIE 0b Master interrupt ena

www.digiembedded.com737USB Controller ModuleHcInterruptDisable registerAddress: 9010 1014Each disable bit in the HcInterruptDisable register correspon

USB host block registers738 NS9750 Hardware ReferenceRegister bit assignmentBits Access Mnemonic Reset DescriptionD31 R/W MIE 0b Master interrupt ena

www.digiembedded.com739USB Controller ModuleHcHCCA registerAddress: 9010 1018The HcHCCA register contains the physical address of the host controller

USB host block registers740 NS9750 Hardware ReferenceHcPeriodCurrentED registerAddress: 9010 101CThe HcPeriodCurrentED register contains the physical

www.digiembedded.com741USB Controller ModuleRegister bit assignmentHcControlHeadED registerAddress: 9010 1020The HcHeadControlED register contains the

USB host block registers742 NS9750 Hardware ReferenceRegister bit assignmentHcControlCurrentED registerAddress: 9010 1024The HcControlCurrentED regis

www.digiembedded.com743USB Controller ModuleRegister bit assignmentHcBulkHeadED registerAddress: 9010 1028The HcBulkHeadED register contains the physi

USB host block registers744 NS9750 Hardware ReferenceRegister bit assignmentHcBulkCurrentED registerAddress: 9010 102CThe HcBulkCurrentED register co

www.digiembedded.com745USB Controller ModuleRegister bit assignmentBits Access Mnemonic Reset DescriptionD31:04 R/W BCED 0h BulkCurrentEDBulkCurrentED

www.digiembedded.com53Working with the CPUNote:In all cases, reading from or writing any data values to any CP15 registers, including those fields spe

USB host block registers746 NS9750 Hardware ReferenceHcDoneHead registerAddress: 9010 1030The HcDoneHead register contains the physical address of th

www.digiembedded.com747USB Controller ModuleHcFmInterval registerAddress: 9010 1034The HcFmInterval register contains the 14-bit value that indicates

USB host block registers748 NS9750 Hardware ReferenceHcFmRemaining registerAddress: 9010 1038The HcFmRemaining register is a 14-bit down counter show

www.digiembedded.com749USB Controller ModuleRegister bit assignmentHcFmNumber registerAddress: 9010 103CThe HcFmNumber register is a 16-bit counter th

USB host block registers750 NS9750 Hardware ReferenceRegister bit assignmentHcPeriodicStart registerAddress: 9010 1040Register bit assignmentBits Acc

www.digiembedded.com751USB Controller ModuleHcLsThreshold registerAddress: 9010 1044The HcLSThreshold register contains a value used by the host contr

USB host block registers752 NS9750 Hardware ReferenceRegister bit assignmentRoot hub partition registersThe remaining USB host block registers are de

www.digiembedded.com753USB Controller ModuleHcRhDescriptorA registerAddress: 9010 1048The HcRhDescriptorA register is the first of two registers descr

USB host block registers754 NS9750 Hardware ReferenceD11 R/W OCPM IS OverCurrentProtectionModeDescribes how the overcurrent status for the root hub p

www.digiembedded.com755USB Controller ModuleHcRhDescriptorB registerAddress: 9010 104CThe HcRhDescriptorB register is the second of two registers desc

System control processor (CP15) registers54 NS9750 Hardware ReferenceAll CP15 register bits that are defined and contain state are set to 0 by reset,

USB host block registers756 NS9750 Hardware ReferenceHcRhStatus registerAddress: 9010 1050The HcRhStatus register has two parts:  The lower word of

www.digiembedded.com757USB Controller ModuleD17 R/W CCIC 0b OverCurrentIndicatorChangeSet by hardware when a change has occurred to the OCI field (bit

USB host block registers758 NS9750 Hardware ReferenceD00 R/W LPS 0b LocalPowerStatus (read)Not supported; always read as 0.ClearGlobalPower (write)In

www.digiembedded.com759USB Controller ModuleHcRhPortStatus[1] registerAddress: 9010 1054The HcRhPortStatus register controls and reports port events o

USB host block registers760 NS9750 Hardware ReferenceD18 R/W PSSC 0b PortSuspendStatusChange0 Resume is not completed1 Resume completedSet when the f

www.digiembedded.com761USB Controller ModuleD09 R/W LSDA Xb LowSpeedDeviceAttached (read)0 Full speed device attached1 Low speed device attachedIndica

USB host block registers762 NS9750 Hardware ReferenceD07:05 N/A Not used N/A Always write to 0.D04 R/W PRS 0b PortResetStatus (read)0 Port reset sign

www.digiembedded.com763USB Controller ModuleD02 R/W PSS 0b PortSuspendStatus (read)0 Port is not suspended1 Port is suspendedIndicates that the port i

USB host block registers764 NS9750 Hardware ReferenceD01 R/W PES 0b PortEnableStatus (read)0 Port is disabled1 Port is enabledIndicates whether the p

www.digiembedded.com765USB Controller ModuleUSB Device Block registersTable 445 provides the addresses of the USB Device Block registers.Device Descri

www.digiembedded.com55Working with the CPUR0: ID code and cache type status registersRegister R0 access the ID register, and cache type register. Read

USB Device Block registers766 NS9750 Hardware ReferenceEndpoint Descriptor #0–#11 registersAddress: 9010 2004 / 2008 / 200C / 2010 / 2014 / 2018 / 20

www.digiembedded.com767USB Controller ModuleUSB Device Endpoint FIFO Control and Data registersTable 447 provides the addresses for the endpoint regis

USB Device Endpoint FIFO Control and Data registers768 NS9750 Hardware ReferenceTable 448 describes the fixed relationship from endpoint to interface

www.digiembedded.com769USB Controller ModuleFIFO Interrupt Status registersThe FIFO Interrupt Status registers contain interrupt status information fo

USB Device Endpoint FIFO Control and Data registers770 NS9750 Hardware ReferenceDevice endpoint statusTable 449 defines the device endpoint status pr

www.digiembedded.com771USB Controller ModuleFIFO Interrupt Status 0 registerAddress: 9010 3000Register bit assignmentFIFO Interrupt Status 1 registerA

USB Device Endpoint FIFO Control and Data registers772 NS9750 Hardware ReferenceRegister bit assignmentBits Access Mnemonic Reset DescriptionD31 RW1T

www.digiembedded.com773USB Controller ModuleFIFO Interrupt Status 2 registerAddress: 9010 3020Register bit assignmentD06 RW1TC NACK3 0 Endpoint 1 nega

USB Device Endpoint FIFO Control and Data registers774 NS9750 Hardware ReferenceD20:16 N/A Reserved N/A Not valid in DMA mode.D15 RW1TC ACK8 0 Endpoi

www.digiembedded.com775USB Controller ModuleFIFO Interrupt Status 3 registerAddress: 9010 3030Register bit assignmentBits Access Mnemonic Reset Descri

vi Interrupt Status Raw ...152Timer Interrupt Status register...

System control processor (CP15) registers56 NS9750 Hardware ReferenceR0: Cache type registerR0: Cache type is a read-only register that contains info

USB Device Endpoint FIFO Control and Data registers776 NS9750 Hardware ReferenceFIFO Interrupt Enable registersThe FIFO Interrupt Enable registers co

www.digiembedded.com777USB Controller ModuleFIFO Interrupt Enable 1 registerAddress: 9010 3014Register bit assignmentBits Access Mnemonic Reset Descri

USB Device Endpoint FIFO Control and Data registers778 NS9750 Hardware ReferenceFIFO Interrupt Enable 2 registerAddress: 9010 3024Register bit assign

www.digiembedded.com779USB Controller ModuleFIFO Interrupt Enable 3 registerAddress: 9010 3034D21 R/W ERROR9 0 Generate an interrupt when ERROR9 in FI

USB Device Endpoint FIFO Control and Data registers780 NS9750 Hardware ReferenceRegister bit assignmentFIFO Packet Control registersAddress: 9010 308

www.digiembedded.com781USB Controller ModuleRegister bit assignmentFIFO Status and Control registersAddress: 9010 3100 / 3108 / 3110 / 3118 / 3120 / 3

USB Device Endpoint FIFO Control and Data registers782 NS9750 Hardware ReferenceRegister bit assignmentBits Access Mnemonic Reset DescriptionD31:24 N

www.digiembedded.com783USB Controller ModuleD15:14 R STATE 0x0 State fieldDefines the state of the endpoint after the most recent communication with t

USB Device Endpoint FIFO Control and Data registers784 NS9750 Hardware Reference

www.digiembedded.com785USB Controller Module

www.digiembedded.com57Working with the CPUDsize and Isize fieldsThe Dsize and Isize fields in the cache type register have the same format, as shown:T

787TimingCHAPTER 17This chapter provides the electrical specifications, or timing, integral to the operation of the NS9750. Timing includes informatio

Electrical characteristics788 NS9750 Hardware ReferenceElectrical characteristicsThe NS9750 operates at a 1.5V core, with 3.3V I/O ring voltages.Abso

www.digiembedded.com789TimingMaximum power dissipationTable 462 shows the maximum power dissipation, including sleep mode information, for I/O and cor

DC electrical characteristics790 NS9750 Hardware ReferenceDC electrical characteristicsDC characteristics specify the worst-case DC electrical perfor

www.digiembedded.com791TimingNotes:1 |(usb_dp) – (usb_dm)|2 Includes VDI range. OutputsAll electrical outputs are 3.3V interface.USB DC electrical out

Reset and edge sensitive input timing requirements792 NS9750 Hardware ReferenceReset and edge sensitive input timing requirementsThe critical timing

www.digiembedded.com793TimingIf an external device driving the reset or edge sensitive input on a Digi processor cannot meet the 500ns maximum rise an

Power sequencing794 NS9750 Hardware ReferencePower sequencingUse these requirements for power sequencing:VDDU3RESET delay is determinedby capacitor o

www.digiembedded.com795TimingMemory timingNote:All AC characteristics are measured with 35pF, unless otherwise noted.Memory timing contains parameters

System control processor (CP15) registers58 NS9750 Hardware ReferenceR1: Control registerRegister R1 is the control register for the ARM926EJ-S proce

Memory timing796 NS9750 Hardware ReferenceSDRAM burst read (16-bit)Figure 104: SDRAM burst read (16-bit) timingNotes:1 This is the bank and RAS addre

www.digiembedded.com797TimingSDRAM burst read (16-bit), CAS latency = 3Figure 105: SDRAM burst read (16-bit), CAS latency = 3 timingNotes:1 This is th

Memory timing798 NS9750 Hardware ReferenceSDRAM burst write (16-bit)Figure 106: SDRAM burst write (16-bit) timingNotes:1 This is the bank and RAS add

www.digiembedded.com799TimingSDRAM burst read (32-bit)Figure 107: SDRAM burst read (32-bit) timingNotes:1 This is the bank and RAS address.2 This is t

Memory timing800 NS9750 Hardware ReferenceSDRAM burst read (32-bit), CAS latency = 3Figure 108: SDRAM burst read (32-bit), CAS latency = 3 timingNote

www.digiembedded.com801TimingSDRAM burst write (32-bit)Figure 109: SDRAM burst write (32-bit) timingNotes:1 This is the bank and RAS address.2 This is

Memory timing802 NS9750 Hardware ReferenceSDRAM load mode Figure 110: SDRAM load mode timingM4M9M8M7M5op codeclk_out<3:0>dy_cs_n<3:0>* ra

www.digiembedded.com803TimingSDRAM refresh modeFigure 111: SDRAM refresh mode timingClock enable timingFigure 112: Clock enable timingprechg CS0 rf CS

Memory timing804 NS9750 Hardware ReferenceTable 468 describes the values shown in the SRAM timing diagrams (Figure 113 through Figure 118).Notes:1 Th

www.digiembedded.com805TimingStatic RAM read cycles with 0 wait statesFigure 113: Static RAM read cycles with 0 wait states timing WTRD = 1WOEN = 1

www.digiembedded.com59Working with the CPU[15] L4 Determines whether the T is set when load instructions change the PC.0 Loads to PC set the T bit1 Lo

Memory timing806 NS9750 Hardware ReferenceStatic RAM asynchronous page mode read, WTPG = 1Figure 114: Static RAM asynchronous page mode read, WTPG =

www.digiembedded.com807TimingStatic RAM read cycle with configurable wait statesFigure 115: Static RAM read cycle with configurable wait states WTRD

Memory timing808 NS9750 Hardware ReferenceStatic RAM sequential write cyclesFigure 116: Static RAM sequential write cycles WTWR = 0WWEN = 0 During

www.digiembedded.com809TimingStatic RAM write cycleFigure 117: Static RAM write cycle WTWR = 0WWEN = 0 During a 32-bit transfer, all four byte_lane

Memory timing810 NS9750 Hardware ReferenceStatic write cycle with configurable wait statesFigure 118: Static write cycle with configurable wait state

www.digiembedded.com811TimingSlow peripheral acknowledge timingThis table describes the values shown in the slow peripheral acknowledge timing diagram

Memory timing812 NS9750 Hardware ReferenceSlow peripheral acknowledge readSlow peripheral acknowledge writeM32 M26M17 M18M19M20M31M27 M28M23 M24M29 M

www.digiembedded.com813TimingEthernet timingNote:All AC characteristics are measured with 10pF, unless otherwise noted.Table 470 describes the values

Ethernet timing814 NS9750 Hardware ReferenceEthernet MII timingFigure 119: Ethernet MII timingE6E5E4E3E2E1E7E7E13E12E11tx_clktxd[3:0],tx_en,tx_er rx_

www.digiembedded.com815TimingEthernet RMII timingFigure 120: Ethernet RMII timingE6E5E4E10E9E8E7E7ref_clktxd[1:0],tx_enrxd[1:0],crs,rx_er mdcmdio (in

System control processor (CP15) registers60 NS9750 Hardware ReferenceThe M, C, I, and RR bits directly affect ICache and DCache behavior, as shown:If

PCI timing816 NS9750 Hardware ReferencePCI timingNote:All AC characteristics are measured with 10pF, unless otherwise noted.Table 471 and Table 472 d

www.digiembedded.com817TimingNotes:1 Minimum times are specified with 0pf and maximum times are specified with 30pf.2 pci_clk_out high and low times s

PCI timing818 NS9750 Hardware ReferenceInternal PCI arbiter timingFigure 121: Internal PCI arbiter timingPCI burst write from NS9750 timingFigure 122

www.digiembedded.com819TimingPCI burst read from NS9750 timingFigure 123: PCI burst read from NS9750 timingNote:The functional timing for trdy_n, devs

PCI timing820 NS9750 Hardware ReferencePCI burst read to NS9750 timingFigure 125: PCI burst read to NS9750 timingNote:The functional timing for valid

www.digiembedded.com821TimingI2C timingNote:All AC characteristics are measured with 10pF, unless otherwise noted.Table 473 describes the values shown

LCD timing822 NS9750 Hardware ReferenceLCD timingNote:All AC characteristics are measured with 10pF, unless otherwise noted.Table 474 describes the v

www.digiembedded.com823TimingNotes:1 CLCDCLK is selected from 5 possible sources:— lcdclk/2 (lcdclk is an external oscillator)— AHB clock— AHB clock/2

LCD timing824 NS9750 Hardware Reference5 These data widths are supported:— 4-bit mono STN single panel— 8-bit mono STN single panel— 8-bit color STN

www.digiembedded.com825TimingVertical timing for STN displaysFigure 130: Vertical timing parameters for STN displaysHorizontal timing for TFT displays

www.digiembedded.com61Working with the CPUR2: Translation Table Base registerRegister R2 is the Translation Table Base register (TTBR), for the base a

LCD timing826 NS9750 Hardware ReferenceHSYNC vs VSYNC timing for STN displaysFigure 133: HSYNC vs VSYNC timing for STN displaysHSYNC vs VSYNC timing

www.digiembedded.com827TimingSPI timingNote:All AC characteristics are measured with 10pF, unless otherwise noted.Table 475 describes the values shown

SPI timing828 NS9750 Hardware ReferenceNotes:1 Active level of SPI enable is inverted (that is, 1) if the CSPOL bit in Serial ChannelB/A/C/D Control

www.digiembedded.com829Timing6 Cload = 10pf for all outputs.7 SPI data order can be reversed such that LSB is first. Use the BITORDR bit in Serial Cha

SPI timing830 NS9750 Hardware ReferenceSPI slave mode 0 and 1: 2-byte transfer(see note 7)Figure 138: SPI slave mode 0 and 1 (2-byte transfer)SPI sla

www.digiembedded.com831TimingIEEE 1284 timingNote:All AC characteristics are measured with 10pF, unless otherwise noted.Table 476 describes the values

USB timing832 NS9750 Hardware ReferenceUSB timingTable 477 and Table 478 describe the values shown in the USB timing diagrams(Figure 141 through Figu

www.digiembedded.com833TimingUSB differential data timingFigure 141: USB differential dataUSB full speed load timingFigure 142: USB full speed loadU11

USB timing834 NS9750 Hardware ReferenceUSB low speed loadFigure 143: USB low speed loadCL = 200pf to 600pfRSusb_dpRSusb_dmLow Speed BufferRs - extern

www.digiembedded.com835TimingReset and hardware strapping timingNote:All AC characteristics are measured with 10pF, unless otherwise noted.Table 479 d

System control processor (CP15) registers62 NS9750 Hardware ReferenceEach two-bit field defines the access permissions for one of the 16 domains (D15

JTAG timing836 NS9750 Hardware ReferenceJTAG timingNote:All AC characteristics are measured with 10pF, unless otherwise noted.Table 480 describes the

www.digiembedded.com837TimingClock timingNote:All AC characteristics are measured with 10pF, unless otherwise noted.The next three timing diagrams per

Clock timing838 NS9750 Hardware ReferenceLCD input clock timingTable 482 describes the values shown in the LCD input clock timing diagram(Figure 147)

www.digiembedded.com839TimingSystem PLL bypass mode timingTable 483 describes the values shown in the system PLL bypass mode timing diagram (Figure 14

841PackagingCHAPTER 18The NS9750 is a complete system-on-chip processor, and includes Ethernet, display support, and a robust peripheral set. NS9750 d

842 NS9750 Hardware ReferenceFigure 149 displays the top view and dimensions of the NS9750. Figure 150 displays the side and bottom views and dimensi

www.digiembedded.com843PackagingFigure 150: NS9750 side and bottom views0.20S//0.35S0.6 + 0.12.46 MAXSABCDEFGHJKLMNPRTUVWYAAABACADAEAF234 561 7 8 9 10

844 NS9750 Hardware ReferenceFigure 151 shows the layout of the NS9750, for use in setting up the board.Figure 151: NS9750 BGA layoutMDCAF23D21DCSn_2

www.digiembedded.com845PackagingProduct specificationsThese tables provide additional information about the NS9750.ROHS substance PPM levelLead 0Mercu

www.digiembedded.com63Working with the CPUFigure 16 shows the format of the Fault Status registers. Table 24 describes the Fault Status register bits.