
NS9750B-A1 Features
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NS9750B-A1 Features
32-bit ARM926EJ-S RISC processor
125 to 200 MHz
5-stage pipeline with interlocking
Harvard architecture
8 kB instruction cache and 4 kB data cache
32-bit ARM and 16-bit Thumb instruction
sets. Can be mixed for performance/code
density tradeoffs
MMU to support virtual memory-based OSs
such as Linux, WinCE/Pocket PC, VxWorks,
others
DSP instruction extensions, improved
divide, single cycle MAC
ARM Jazelle, 1200CM (coffee marks) Java
accelerator
EmbeddedICE-RT debug unit
JTAG boundary scan, BSDL support
External system bus interface
32-bit data, 32-bit internal address bus,
28-bit external address bus
Glueless interface to SDRAM, SRAM,
EEPROM, buffered DIMM, Flash
4 static and 4 dynamic memory chip
selects
1-32 wait states per chip select
A shared Static Extended Wait register
allows transfers to have up to 16368
wait states that can be externally
terminated.
Self-refresh during system sleep mode
Automatic dynamic bus sizing to 8 bits, 16
bits, 32 bits
Burst mode support with automatic data
width adjustment
Two external DMA channels for external
peripheral support
System Boot
High-speed boot from 8-bit, 16-bit, or
32-bit ROM or Flash
Hardware-supported low cost boot from
serial EEPROM through SPI port (patent
pending)
High performance 10/100 Ethernet MAC
10/100 Mbps MII/RMII PHY interfaces
Full-duplex or half-duplex
Station, broadcast, or multicast address
filtering
2 kB RX FIFO
256 byte TX FIFO with on-chip buffer
descriptor ring
– Eliminates underruns and decreases
bus traffic
Separate TX and RX DMA channels
Intelligent receive-side buffer size
selection
Full statistics gathering support
External CAM filtering support
PCI/CardBus port
PCI v2.2, 32-bit bus, up to 33 MHz bus
speed
Programmable to:
– PCI device mode
– PCI host mode:
Supports up to 3 external PCI
devices
Embedded PCI arbiter or external
arbiter
CardBus host mode
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