Digi NS9750 Bedienungsanleitung PDF herunterladen (Seite 9)

System configuration

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System configuration

The PLL and other system settings can be configured at powerup before the CPU boots. External

pins configure the necessary control register bits at powerup. External pulldown resistors can be

used to configure the PLL and system configuration registers depending on the application. The

recommended value is 2.2k ohm to 2.4k ohm.

This table describes how each bit is used to configure the powerup settings, where 1 indicates the

internal pullup resistor and 0 indicates an external pulldown resistor. Table 2 shows

PLL ND[4:0]

multiplier values. Figure 9, "NS9750B-A1 BGA layout," on page 82 shows the bootstrap pins.

Pin name Configuration bits

rtck PCI arbiter configuration

0External PCI arbiter

1 Internal PCI arbiter

boot_strap[0] Chip select 1 byte_lane_enable_n/write_enable_n configuration bootstrap

select

0 byte_lane_enable_n (2.4K pulldown added)

1 write_enable_n for byte-wide devices (default)

boot_strap[4:3] Chip select 1 data width bootstrap select

00 16 bits

01 8 bits

11 32 bits

boot_strap[2] Memory interface read mode bootstrap select

Note: An external pulldown resistor must be used; this selects command

delayed mode. Clock delayed mode is reserved for future use.

0 Command delayed mode

Commands are launched on a 90-degree phase-shifted AHB clock, and

AHB clock is routed to the external dynamic memory.

1 Clock delayed mode

Reserved for future use.

boot_strap[1] CardBus mode bootstrap select

0 CardBus mode

1 PCI mode

gpio[49] Chip select polarity

0 Active high

1 Active low

gpio[44] Endian mode

0 Big Endian

1 Little Endian

reset_done Bootup mode

0 Boot from SDRAM using serial SPI EEPROM

1 Boot from flash/ROM

Table 1: Configuration pins— Bootstrap initialization

1 2 3 4 5 6 7 8 9 10 11 12 13 14 ... 87 88

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