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NS9750B-A1 Datasheet 03/2006
Figure 9 shows the layout of the NS9750B-A1, for use in setting up the board.
For information about hardware strapping options, see Table 1, “Configuration pins— Bootstrap
initialization,” on page 5.
Figure 9: NS9750B-A1 BGA layout
AF2
H1
CKE_1
J2
GPIO41
DQM_2
H
A15
D12
A14
AD8
T23
P26
AD10
R14
W1
C
GPIO23
AD1
= HW Strap Option
Y4
REQn_1
AD29
AC3
B7
D25
GPIO17
N24
VDDS
VDDS
VSS
Y
B1
AE18 AD18
A9
A16
VSS
VSS
(NC2)
AA23
RXD_2
AE1
BLSn_2
E26
D11
AF20
K24
VSS
V4
U25
REQn_2
GPIO32
AE24
G23
DQM_3
D2
K
A13
GPIO21
D17
R13
GPIO44
SCSn_2
B20
PAR
A24
E4
AE13
A11
D19
VSS
C3
R26
AB23
AC5
AE26
GPIO48
D5
D24
USB_X1
D16
AF18
AD20
VSS
VSS
VSS
AA
F24
AD17
AE15
VDDC
VSS
VSS
(NC5)
AA24
NS9750B-A1, 388 BGA
E2
WEn
AE20
N16
U2
U26
AD18
AF7
D30
R1
H4
M1
B10
P14
20
AD4
VDDC
BLSn_1
A26
AE10
P13
GPIO28
INTDn
AD26
D15
H25
AB24
GPIO30
AD22
AC1
CKE_0
BSTR_2
N4
A12
CBEn_0
VDDS
VSS
VSS
VSS
AB
25
D0
C19
VDDC
VDDS
VSS
(GND)
(GND)
GNTn_3
E3
C23
R4
AF13
U3
TXEN
AD20
AC6
AD8
D23
N1
( ) = Reserved
MDIO
G24
A3
AD2
AF6
DQM_0
R2
C14
AD13
M26
VSS
AA1
SCANENn
GNTn_2
C25
C26
16
AD15
AB25
AF5
AD4
(GND)
GPIO18
C18
N23
VDDS
VSS
VSS
T15
AF24
AE2
AC
8
G3
D31
AC20
VDDC
VDDS
VSS
(GND)
(GND)
DQM_1
A9
J1
AF12
D14
AC18
J24
U4
TXER
AD17
GPIO27
D9
J4
AC15
AA25
MDC (GND)
C13
A1
AD14
AD5
CASn
SCSn_1
GPIO4
T14
AD21
PLLTSTn
AD30
CKO_3
AD12
A6
B16
AD9
AD13
AB26
F25
(GND)
AF17
VDDS
M14
VSS
AE9
INTBn
AD
D17
C1
CKO_1
11
VDDC
VDDC
VSS
VSS
(GND)
(GND)
VSS
7
M4
BSTR_1
SPLL_AV
W23
TXD_0
FRAMEn
AE4
D27
B22
VSS
AA26
GPIO47
A1
P2
AE12
BISTENn
J26
D20
M13
AE21
REQn_3
CLK_IN
A4
C21
AC13
A7
4
E24
P4
M
VSS
VSS
COL
AE
D1
B24
P
B11
AE17
VSS
VSSVSS
VSS
(GND)
(GND)
VSS
D29
USB_X2
K3
LCD_CLK
I2C_SCL
VSS
W24
AD16
AF23
AC2
C5
F2
23
T1
AD10
D18
N11
Y23
AD21
AF8
DCSn_3
A17
C20
J23P23
AE7
GPIO35
DCSn_1
TMS
DEVSELn
CBEn_1
L14
D26
D28
A22
D12
C8
AF11
AC10
L13
VSS
AB2
AF1
AF
D3
A21
AD15
T26
R25
VSS
VDDCVDDS VSS
(GND)
NC3
GPIO38
GPIO45
D26
T4
J
M25
VSS
VSS
U1
W25
IDSEL
AF26
E23 B23
SRST_EN
A6
L3
AC14
A16
GPIO7
R23
VSS
VSS
Y24
TXD_2
AD22
GPIO34
A22
AC7
AC22
AF21
AF16
A15
AD25
A8
C2
AC24
F4
BLSn_3
B2
DY_PWRn
T
GPIO22
AC12
A4
VSS
R16
AB3
AE23
GPIO39
6
CKE_3
AC19
B18
H26
VDDC
VDDCVDDS VSS
(GND)
A7
H3
VDDS
VSS
N15
W26
AD23
5
D19
K1
C12
M23
AD3
VSS VSS
Y25
TXD_1
AD26
AD7
BLSn_0
A25
GPIO3
RESETn
VSS
AE22
D6
Top View, Balls Facing Down
B13
AC17
17
A
B25
GPIO19
D2
24
D
B14
C10
D13
C17
N14
VSS
AB4
GPIO49
AF3
B6
P3
BSTR_4
BSTR_3
SPLL_DV
J25L25
VDDC
VDDCVDDS
(GND)
AE25
D22
T2
A24
A11
TCK
VDDS
VSS
T11
VSS
V23
B21
AD7
VSS VSS
Y26
TXD_3
CBEn_3
GPIO40
GPIO33 SYS_X1
B19
GPIO2
AD5
AD24
1
D8
A19
C15
D25
F26
BSTR_0
L1
GPIO14
R24
V1
GPIO37
AE3
C4
26
D13
B12
C11
GPIO9
R15 P15
AA2
AF4
G
K2
J3
RTCK
VDDC
VDDS(VDDC)
AD23
E
GPIO25
A10
15
TRSTn
VDDS
A3
VSS
P11
VSS
NC2
INTAn
E25T25
M12
W2
RXER
AD24
AE8
D16
B17
18
K26
L24
AD19
D7
D8
C9
DCSn_0
T3
GPIO11
C16
T13
B3
G2
13
AC11
AD6
AE5
AD2
G1
3
A21
H2
A20
D1
P16
VSS
AA3
AF9
AD31
B5
AE11
TDI
K23
VSS
VSS
(VDDS)
GPIO36
D21
GPIO0
PERRn
VDDC
VDDS
A2
VSS
T12
VSS
D3
A25
A10
P24
W3
RXDV
AD27
AD6
DCSn_2
AD19
A13
H24
VSS
Y1
V24
CRS
NC1
G4
D6
F23
M3
GPIO16
A5
AE16
VSS
SRSTn
C6
SCSn_0
AD0
A0
F3
L
RXCLK
T24
T16
U
AD14
TDO
GPIO1
VDDC
VSS
AC8
INTCn
B8
F1
GPIO10
L23
VSS
VSS
VSS
VDDS = I/O = 3.3V
R12
M16
B26
12
AC16
N26
W4
TXCLK
PCI_CKO
C24
N2
19
D20
VSS
V25
GPIO46
D18
SYS_X2
A5
GPIO12
AF15
VSS
VSS
RSC_IN
CKO_2
D10
R3
P1
10
14
P25
VSS
AB1
D4
TA_STB
SERRn
V
D15
VDDC
AA4
AC9
GPIO31
AC25
PHY_INTn
SCSn_3
G26
AF10
TRDYn
VDDS
VSS
VSS
VDDC = CORE = 1.5V
P12
VSS
B9
A14
(NC1)
V2
RXD_0
AC21
RASn
D5
AE19
SPLL_DG
M11
V26
PCI_CKI
A23
E1
2
L4
GPIO26
A12
L11
PCI_RSTn
D22
D21
(GND)
(GND)
N3
GPIO13
IRDYn
GNTn_1
AC4
D11
CKO_0
GPIO15
B15
L26
AE6
G25
AE14
A19
AD11
Y2
AC23
AD3
D4
D7
L2
N25
STOPn
VDDS
VDDS
VSS
VSS = GROUND RETURN
R11
M15 L15
RST_DONE
GPIO43
GPIO8
A17
AF19
SPLL_AG
A20
K25
VSS
(NC4)
RXD_1
CKE_2
ST_OEn
C7
GPIO5
GPIO6 A8
L12
U23
AD28 CBEn_2
B4
D9
R
AD11
A23VSS
GPIO42
C22
D14
M2
N
K4
GPIO24
AD1
9
AF14
D10
M24
H23
AD12
VSS
N13
GPIO29
D24
A18
A27
Y3
AC26
USB_DP
22
VSS
VDDS
VSS
VDDS
L16
USB_DM
AF22
W
21
A2
AD16
A18
I2C_SDA
VDDC
VSS
(NC3)
RXD_3
A26
B
V3
U24
AD25
AD9
AF25
F
D23
GPIO20
N12
V1.3
- NS9750B-A1 Datasheet 1
- Contents 3
- NS9750B-A1 Datasheet 03/2006 4
- NS9750B-A1 Features 5
- 2 6
- System-level interfaces 8
- System configuration 9
- Table 2: PLL ND[4:0] 10
- Pin name Configuration bits 10
- General Purpose ID register 11
- System boot 12
- System Clock 13
- NS9750B-A1 14
- USB clock 15
- System Memory interface 16
- Pin # Signal Name 17
- I/O Description 17
- Name I/O Description 20
- Ethernet interface 22
- Clock generation/system pins 23
- PCI interface 24
- PCI/CardBus signals 26
- 24 28
- GPIO MUX 29
- Pin # Signal name 30
- Table 12: GPIO MUX pinout 30
- USB Power 35
- Controller 35
- CLSTN[0] 36
- MLSTN[0] 36
- CUSTN[0] 37
- RED[0] 38
- GREEN[0], BLUE[0] 38
- C interface 39
- USB Interface 39
- Reserved pins 41
- Address and register maps 42
- BBus peripheral address map 43
- Electrical characteristics 44
- Maximum power dissipation 45
- Typical power dissipation 45
- DC electrical characteristics 46
- USB DC electrical outputs 47
- 44 48
- Power sequencing 49
- Memory timing 50
- SDRAM burst read (16-bit) 51
- SDRAM burst write (16-bit) 52
- SDRAM burst read (32-bit) 52
- SDRAM burst write (32-bit) 53
- SDRAM load mode 54
- SDRAM refresh mode 54
- Clock enable timing 54
- SRAM timing 55
- 52 56
- WTWR = from 0 to 15 60
- 57 61
- 58 62
- Ethernet timing 63
- Ethernet MII timing 64
- Ethernet RMII timing 64
- PCI timing 65
- Internal PCI arbiter timing 66
- 64 68
- C timing 69
- LCD timing 70
- 68 72
- LCD output timing 73
- SPI timing 74
- 72 76
- IEEE 1284 timing 77
- USB timing 78
- USB full speed load 79
- USB low speed load 79
- 80
- JTAG timing 81
- Clock timing 82
- 79 83
- Packaging 84
- NS9750B-A1, 388 BGA 86
- Product specifications 87
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